From: Conor Dooley <conor@kernel.org>
To: palmer@dabbelt.com
Cc: Yangyu Chen <cyy@cyyself.name>,
Conor Dooley <conor.dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v1 7/7] RISC-V: always report presence of Zicsr/Zifencei
Date: Thu, 4 May 2023 21:38:49 +0100 [thread overview]
Message-ID: <20230504-chemist-charter-f572af461fcf@spud> (raw)
In-Reply-To: <20230504-oncoming-antihero-1ed69bb8f57d@spud>
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On Thu, May 04, 2023 at 07:14:26PM +0100, Conor Dooley wrote:
> @@ -204,8 +204,10 @@ arch_initcall(riscv_cpuinfo_init);
> * New entries to this struct should follow the ordering rules described above.
> */
> static struct riscv_isa_ext_data isa_ext_arr[] = {
> + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
Heh, well that is not the right order, per the rules I wrote in the
comment above. Whoops...
> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
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next prev parent reply other threads:[~2023-05-04 21:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-04 18:14 [PATCH v1 0/7] ISA string parser cleanups++ Conor Dooley
2023-05-04 18:14 ` [PATCH v1 1/7] RISC-V: simplify register width check in ISA string parsing Conor Dooley
2023-05-05 7:04 ` Andrew Jones
2023-05-04 18:14 ` [PATCH v1 2/7] RISC-V: only iterate over possible CPUs in ISA string parser Conor Dooley
2023-05-05 7:07 ` Andrew Jones
2023-05-04 18:14 ` [PATCH v1 3/7] RISC-V: split early & late of_node to hartid mapping Conor Dooley
2023-05-04 18:14 ` [PATCH v1 4/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing Conor Dooley
2023-05-05 7:40 ` Andrew Jones
2023-05-05 7:51 ` Conor Dooley
2023-05-05 12:40 ` Yangyu Chen
2023-05-05 13:04 ` Conor Dooley
2023-05-04 18:14 ` [PATCH v1 5/7] RISC-V: rework comments in ISA string parser Conor Dooley
2023-05-05 9:12 ` Andrew Jones
2023-05-04 18:14 ` [PATCH v1 6/7] RISC-V: remove decrement/increment dance " Conor Dooley
2023-05-05 11:01 ` Andrew Jones
2023-05-04 18:14 ` [PATCH v1 7/7] RISC-V: always report presence of Zicsr/Zifencei Conor Dooley
2023-05-04 20:38 ` Conor Dooley [this message]
2023-05-05 11:11 ` Andrew Jones
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