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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id md8-20020a170906ae8800b0095390b1dd39sm809334ejb.115.2023.05.05.04.11.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 04:11:43 -0700 (PDT) Date: Fri, 5 May 2023 13:11:42 +0200 From: Andrew Jones To: Conor Dooley Subject: Re: [PATCH v1 7/7] RISC-V: always report presence of Zicsr/Zifencei Message-ID: <20230505-bfc5ac83cc446364b06cceeb@orel> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> <20230504-oncoming-antihero-1ed69bb8f57d@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230504-oncoming-antihero-1ed69bb8f57d@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230505_041146_784302_BAF129B5 X-CRM114-Status: GOOD ( 19.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yangyu Chen , Conor Dooley , palmer@dabbelt.com, Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, May 04, 2023 at 07:14:26PM +0100, Conor Dooley wrote: > From: Conor Dooley > > Zicsr/Zifencei were part of i when the port was written and are required > by the kernel. There's not much that userspace can do with this extra > information, but there is no harm in reporting an ISA string that closer > resembles the current versions of the ISA specifications either. > > Signed-off-by: Conor Dooley > --- > arch/riscv/include/asm/hwcap.h | 2 ++ > arch/riscv/kernel/cpu.c | 2 ++ > arch/riscv/kernel/cpufeature.c | 7 +++++++ > 3 files changed, 11 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 9af793970855..aa61031f7923 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -44,6 +44,8 @@ > #define RISCV_ISA_EXT_ZIHINTPAUSE 32 > #define RISCV_ISA_EXT_SVNAPOT 33 > #define RISCV_ISA_EXT_ZICBOZ 34 > +#define RISCV_ISA_EXT_ZICSR 35 > +#define RISCV_ISA_EXT_ZIFENCEI 36 > > #define RISCV_ISA_EXT_MAX 64 > #define RISCV_ISA_EXT_NAME_LEN_MAX 32 > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index b0c3ec0f2f5b..0d5d580dca61 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -204,8 +204,10 @@ arch_initcall(riscv_cpuinfo_init); > * New entries to this struct should follow the ordering rules described above. > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), > __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), > __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), > + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index b425658bbf08..92f0e7b78eef 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -292,6 +292,13 @@ void __init riscv_fill_hwcap(void) > #undef SET_ISA_EXT_MAP > } > > + /* > + * Linux requires Zicsr & Zifencei, so we may as well always > + * set them. > + */ > + set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); > + set_bit(RISCV_ISA_EXT_ZICSR, this_isa); > + > /* > * All "okay" hart should have same isa. Set HWCAP based on > * common capabilities of every "okay" hart, in case they don't > -- > 2.39.2 > Besides the ordering you pointed out, Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv