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boundary="===============3867858972209332169==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============3867858972209332169== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="k34rdV1i7X0SFuIK" Content-Disposition: inline --k34rdV1i7X0SFuIK Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 05, 2023 at 09:40:22AM +0200, Andrew Jones wrote: > On Thu, May 04, 2023 at 07:14:23PM +0100, Conor Dooley wrote: > > From: Conor Dooley > >=20 > > Since riscv_fill_hwcap() now only iterates over possible cpus, the > > basic validation of whether riscv,isa contains "rv" can be moved > > to riscv_early_of_processor_hartid(). > >=20 > > Further, "ima" support is required by the kernel, so reject any CPU not > > fitting the bill. > > > > Signed-off-by: Conor Dooley > > --- > > arch/riscv/kernel/cpu.c | 8 +++++--- > > arch/riscv/kernel/cpufeature.c | 12 ++++++------ > > 2 files changed, 11 insertions(+), 9 deletions(-) > >=20 > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index 7030a5004f8e..b0c3ec0f2f5b 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -63,10 +63,12 @@ int riscv_early_of_processor_hartid(struct device_n= ode *node, unsigned long *har > > pr_warn("CPU with hartid=3D%lu has no \"riscv,isa\" property\n", *ha= rt); > > return -ENODEV; > > } > > - if (tolower(isa[0]) !=3D 'r' || tolower(isa[1]) !=3D 'v') { > > - pr_warn("CPU with hartid=3D%lu has an invalid ISA of \"%s\"\n", *har= t, isa); > > + > > + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) > > + return -ENODEV; > > + > > + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) >=20 > 'ima' matches the DT binding pattern requirement and the order required > by 27.11 "Subset Naming Convention". Aye, perhaps I should have mentioned it in my commit message that those particular orders are required by the dt-binding. If the ACPI series lands before this one does, since I'll have to rebase anyway, I'll add a mention of the ACPI spec's position. > If the spec ever squeezes more single > letter extensions into the front of the ISA string, then we can cross > that bridge when we get to it. Perhaps by then we have evolved beyond needing the ISA string! (A boy can dream) > > return -ENODEV; > > - } > > =20 > > return 0; > > } > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeat= ure.c > > index 3ae456413f79..a79c5c52a174 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -130,12 +130,12 @@ void __init riscv_fill_hwcap(void) > > continue; > > } > > =20 > > - if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4)) > > - continue; > > - > > - if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4)) > > - continue; > > - > > + /* > > + * For all possible cpus, we have already validated in > > + * the boot process that they at least contain "rv" and > > + * whichever of "32"/"64" this kernel supports, and so this > > + * section can be skipped. > > + */ > > isa +=3D 4; >=20 > When we add RV128 support this will need a tweak, but that's for another > day. Yeah, adding 128-bit is so far off that it's not worth considering, but easily handled in this particular location. > Since all ISA strings must start with rvXX per the spec, then this > works for ACPI too, which states the isa string in its ISA string table > must conform to the unpriv spec. >=20 > > =20 > > bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); > > --=20 > > 2.39.2 > >=20 >=20 > Reviewed-by: Andrew Jones Thanks! --k34rdV1i7X0SFuIK Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZFS1lAAKCRB4tDGHoIJi 0sLYAQC0MDUbIwjDlPXiztHtt3oLN4e0tNqqJqCFE3liZhRZ6QD/for1s/2KG3vM 1EFRrM8t0bXhojx2hJvkxWtXwEnE7go= =bced -----END PGP SIGNATURE----- --k34rdV1i7X0SFuIK-- --===============3867858972209332169== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============3867858972209332169==--