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From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor@kernel.org>
Cc: Yangyu Chen <cyy@cyyself.name>,
	Conor Dooley <conor.dooley@microchip.com>,
	palmer@dabbelt.com, Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v1 2/7] RISC-V: only iterate over possible CPUs in ISA string parser
Date: Fri, 5 May 2023 09:07:51 +0200	[thread overview]
Message-ID: <20230505-ecf405ab513637ed8e3a7435@orel> (raw)
In-Reply-To: <20230504-simple-chant-c33c14cc9e4e@spud>

On Thu, May 04, 2023 at 07:14:21PM +0100, Conor Dooley wrote:
> From: Sunil V L <sunilvl@ventanamicro.com>
> 
> During boot we call riscv_of_processor_hartid() for each hart that we
> add to the possible cpus list. Repeating the call again here is not
> required, if we iterate over the list of possible CPUs, rather than the
> list of all CPUs.
> 
> The call to of_property_read_string() for "riscv,isa" cannot fail
> either, as it has previously succeeded in riscv_of_processor_hartid(),
> but leaving in the error checking makes the operation of the loop more
> obvious & provides leeway for future refactoring of
> riscv_of_processor_hartid().
> 
> Partially ripped from Sunil's ACPI support series, with the logic
> inverted to continue early on failure.
> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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  reply	other threads:[~2023-05-05  7:08 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-04 18:14 [PATCH v1 0/7] ISA string parser cleanups++ Conor Dooley
2023-05-04 18:14 ` [PATCH v1 1/7] RISC-V: simplify register width check in ISA string parsing Conor Dooley
2023-05-05  7:04   ` Andrew Jones
2023-05-04 18:14 ` [PATCH v1 2/7] RISC-V: only iterate over possible CPUs in ISA string parser Conor Dooley
2023-05-05  7:07   ` Andrew Jones [this message]
2023-05-04 18:14 ` [PATCH v1 3/7] RISC-V: split early & late of_node to hartid mapping Conor Dooley
2023-05-04 18:14 ` [PATCH v1 4/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing Conor Dooley
2023-05-05  7:40   ` Andrew Jones
2023-05-05  7:51     ` Conor Dooley
2023-05-05 12:40   ` Yangyu Chen
2023-05-05 13:04     ` Conor Dooley
2023-05-04 18:14 ` [PATCH v1 5/7] RISC-V: rework comments in ISA string parser Conor Dooley
2023-05-05  9:12   ` Andrew Jones
2023-05-04 18:14 ` [PATCH v1 6/7] RISC-V: remove decrement/increment dance " Conor Dooley
2023-05-05 11:01   ` Andrew Jones
2023-05-04 18:14 ` [PATCH v1 7/7] RISC-V: always report presence of Zicsr/Zifencei Conor Dooley
2023-05-04 20:38   ` Conor Dooley
2023-05-05 11:11   ` Andrew Jones

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