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05 May 2023 06:04:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 5 May 2023 06:04:45 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Fri, 5 May 2023 06:04:44 -0700 Date: Fri, 5 May 2023 14:04:25 +0100 From: Conor Dooley To: Yangyu Chen CC: , , , , Subject: Re: [PATCH v1 4/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing Message-ID: <20230505-rural-polymer-b3db3f951aa8@wendy> References: <20230504-sultry-frostlike-9dbf19333725@spud> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230505_140512_326089_52B94E64 X-CRM114-Status: GOOD ( 25.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0789410045104608007==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============0789410045104608007== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="SY5PJMplTQujjuD8" Content-Disposition: inline --SY5PJMplTQujjuD8 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 05, 2023 at 08:40:22PM +0800, Yangyu Chen wrote: > On 5/5/23 2:14 AM, Conor Dooley wrote: > > From: Conor Dooley > > > > Since riscv_fill_hwcap() now only iterates over possible cpus, the > > basic validation of whether riscv,isa contains "rv" can be moved > > to riscv_early_of_processor_hartid(). > > > > Further, "ima" support is required by the kernel, so reject any CPU not > > fitting the bill. > > > > Signed-off-by: Conor Dooley > > --- > > arch/riscv/kernel/cpu.c | 8 +++++--- > > arch/riscv/kernel/cpufeature.c | 12 ++++++------ > > 2 files changed, 11 insertions(+), 9 deletions(-) > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index 7030a5004f8e..b0c3ec0f2f5b 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -63,10 +63,12 @@ int riscv_early_of_processor_hartid(struct device_n= ode *node, unsigned long *har > > pr_warn("CPU with hartid=3D%lu has no \"riscv,isa\" property\n", *ha= rt); > > return -ENODEV; > > } > > - if (tolower(isa[0]) !=3D 'r' || tolower(isa[1]) !=3D 'v') { > > - pr_warn("CPU with hartid=3D%lu has an invalid ISA of \"%s\"\n", *har= t, isa); > > + > > + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) > > + return -ENODEV; > > + > > + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) > > return -ENODEV; > > - } > > =20 > > return 0; > > } >=20 > What about reducing the compare string to "rv32" and "rv64" only? I explicitly wanted the "ima" to rule out harts that might've been left enabled but we cannot run on. > Linux kernel is able to run on RV32IA or RV64IA CPUs theoretically as > someone did before[1]. In this case, M extension is not required here. > Although it's an invalid DT for now, reducing the compare string will > make the porting easier. And M extension does not provide additional > ISA-level registers that need the kernel to care about during context > switch. >=20 > In my opinion, we should concern about if someday linux will support > RV32E or RV64E. It's not necessary to validate if "ima" presents here > for better forward compatibility. >=20 > [1] https://www.facebook.com/groups/riscv.tw/posts/1611033709104137/ I had a look, and as expected, this requires a makefile change to remove the M extension from -march. If that change ever lands in mainline the check here could be modified too, but otherwise I don't think we need to be concerned about what some out of tree code is doing. Cheers, Conor. --SY5PJMplTQujjuD8 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZFT+2QAKCRB4tDGHoIJi 0umHAQDN1yH4QMEypKxDG9yaBoRlfabHrE44IalKVufo+YBjDgD+ItV07+li+xbV OviU0HsXs7LES9xGhEJJXEmOE5UOFAA= =PQ9J -----END PGP SIGNATURE----- --SY5PJMplTQujjuD8-- --===============0789410045104608007== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============0789410045104608007==--