Re: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree

Krzysztof Kozlowski
2023-05-08T09:20:42Z

On 07/05/2023 20:23, Jisheng Zhang wrote:
> Add initial device tree for the light(a.k.a TH1520) RISC-V SoC by
> T-HEAD.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/boot/dts/thead/light.dtsi | 454 +++++++++++++++++++++++++++
> 1 file changed, 454 insertions(+)
> create mode 100644 arch/riscv/boot/dts/thead/light.dtsi
>
> diff --git a/arch/riscv/boot/dts/thead/light.dtsi b/arch/riscv/boot/dts/thead/light.dtsi
> new file mode 100644
> index 000000000000..cdf6d8b04d22
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/light.dtsi
> @@ -0,0 +1,454 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Alibaba Group Holding Limited.
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +/ {
> + compatible = "thead,light";

Undocumented compatible.

Please run scripts/checkpatch.pl and fix reported warnings.

> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <3000000>;
> +
> + c910_0: cpu@0 {
> + compatible = "thead,c910", "riscv";

Probably the same.

(...)

> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + reset: reset-sample {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> + compatible = "thead,reset-sample";

Undocumented compatible.

Please run scripts/checkpatch.pl and fix reported warnings.

> + entry-reg = <0xff 0xff019050>;
> + entry-cnt = <4>;
> + control-reg = <0xff 0xff015004>;
> + control-val = <0x1c>;
> + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
> + };
> +
> + plic: interrupt-controller@ffd8000000 {
> + compatible = "thead,c910-plic";
> + reg = <0xff 0xd8000000 0x0 0x01000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + riscv,ndev = <240>;
> + };
> +
> + clint: timer@ffdc000000 {
> + compatible = "thead,c900-clint";

Undocumented compatible.

Please run scripts/checkpatch.pl and fix reported warnings.

> + reg = <0xff 0xdc000000 0x0 0x00010000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>;
> + };
> +
> + uart0: serial@ffe7014000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7014000 0x0 0x4000>;
> + interrupts = <36>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart1: serial@ffe7f00000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7f00000 0x0 0x4000>;
> + interrupts = <37>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@ffe7f04000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7f04000 0x0 0x4000>;
> + interrupts = <39>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + gpio2: gpio@ffe7f34000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xe7f34000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portc: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <58>;
> + };
> + };
> +
> + gpio3: gpio@ffe7f38000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xe7f38000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portd: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <59>;
> + };
> + };
> +
> + gpio0: gpio@ffec005000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xec005000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porta: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <56>;
> + };
> + };
> +
> + gpio1: gpio@ffec006000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xec006000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portb: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <57>;
> + };
> + };
> +
> + uart2: serial@ffec010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xec010000 0x0 0x4000>;
> + interrupts = <38>;
> + clocks = <&uart_sclk>;
> + clock-names = "baudclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + dmac0: dmac@ffefc00000 {

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

Best regards,
Krzysztof