From: Andrew Jones <ajones@ventanamicro.com>
To: zhangfei <zhang_fei_0403@163.com>
Cc: aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, zhangfei@nj.iscas.ac.cn
Subject: Re: [PATCH] riscv: Optimize memset
Date: Tue, 9 May 2023 11:16:33 +0200 [thread overview]
Message-ID: <20230509-b0dc346928ddc8d2b5690f67@orel> (raw)
In-Reply-To: <20230509022207.3700-3-zhang_fei_0403@163.com>
On Tue, May 09, 2023 at 10:22:07AM +0800, zhangfei wrote:
> From: zhangfei <zhangfei@nj.iscas.ac.cn>
>
> > > 5:
> > > - sb a1, 0(t0)
> > > - addi t0, t0, 1
> > > - bltu t0, a3, 5b
> > > + sb a1, 0(t0)
> > > + sb a1, -1(a3)
> > > + li a4, 2
> > > + bgeu a4, a2, 6f
> > > +
> > > + sb a1, 1(t0)
> > > + sb a1, 2(t0)
> > > + sb a1, -2(a3)
> > > + sb a1, -3(a3)
> > > + li a4, 6
> > > + bgeu a4, a2, 6f
> > > +
> > > + sb a1, 3(t0)
> > > + sb a1, -4(a3)
> > > + li a4, 8
> > > + bgeu a4, a2, 6f
> >
> > Why is this check here?
>
> Hi,
>
> I filled head and tail with minimal branching. Each conditional ensures that
> all the subsequently used offsets are well-defined and in the dest region.
I know. You trimmed my comment, so I'll quote myself, here
"""
After the check of a2 against 6 above we know that offsets 6(t0)
and -7(a3) are safe. Are we trying to avoid too may redundant
stores with these additional checks?
"""
So, again. Why the additional check against 8 above and, the one you
trimmed, checking 10?
>
> Although this approach may result in redundant storage, compared to byte by
> byte storage, it allows storage instructions to be executed in parallel and
> reduces the number of jumps.
I understood that when I read the code, but text like this should go in
the commit message to avoid people having to think their way through
stuff.
>
> I used the code linked below for performance testing and commented on the memset
> that calls the arm architecture in the code to ensure it runs properly on the
> risc-v platform.
>
> [1] https://github.com/ARM-software/optimized-routines/blob/master/string/bench/memset.c#L53
>
> The testing platform selected RISC-V SiFive U74.The test data is as follows:
>
> Before optimization
> ---------------------
> Random memset (bytes/ns):
> memset_call 32K:0.45 64K:0.35 128K:0.30 256K:0.28 512K:0.27 1024K:0.25 avg 0.30
>
> Medium memset (bytes/ns):
> memset_call 8B:0.18 16B:0.48 32B:0.91 64B:1.63 128B:2.71 256B:4.40 512B:5.67
> Large memset (bytes/ns):
> memset_call 1K:6.62 2K:7.02 4K:7.46 8K:7.70 16K:7.82 32K:7.63 64K:1.40
>
> After optimization
> ---------------------
> Random memset bytes/ns):
> memset_call 32K:0.46 64K:0.35 128K:0.30 256K:0.28 512K:0.27 1024K:0.25 avg 0.31
> Medium memset (bytes/ns )
> memset_call 8B:0.27 16B:0.48 32B:0.91 64B:1.64 128B:2.71 256B:4.40 512B:5.67
> Large memset (bytes/ns):
> memset_call 1K:6.62 2K:7.02 4K:7.47 8K:7.71 16K:7.83 32K:7.63 64K:1.40
>
> From the results, it can be seen that memset has significantly improved its performance with
> a data volume of around 8B, from 0.18 bytes/ns to 0.27 bytes/ns.
And these benchmark results belong in the cover letter, which this series
is missing.
Thanks,
drew
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next prev parent reply other threads:[~2023-05-09 9:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 8:43 [PATCH] riscv: Optimize memset 张飞
2023-05-05 11:54 ` Andrew Jones
2023-05-09 2:22 ` [PATCH 1/2] RISC-V: lib: Improve memset assembler formatting zhangfei
2023-05-09 2:22 ` [PATCH 2/2] riscv: Optimize memset zhangfei
2023-05-09 2:22 ` Re: [PATCH] " zhangfei
2023-05-09 9:16 ` Andrew Jones [this message]
2023-05-10 3:52 ` [PATCH 0/2] riscv: Optimize memset for data sizes less than 16 bytes zhangfei
2023-05-10 3:52 ` [PATCH 1/2] RISC-V: lib: Improve memset assembler formatting zhangfei
2023-05-10 7:13 ` Conor Dooley
2023-05-11 1:55 ` zhangfei
2023-05-10 3:52 ` [PATCH 2/2] riscv: Optimize memset zhangfei
2023-05-10 3:52 ` [PATCH] " zhangfei
2023-05-10 6:58 ` Andrew Jones
2023-05-11 1:42 ` zhangfei
2023-05-09 9:48 ` [PATCH 1/2] RISC-V: lib: Improve memset assembler formatting Andrew Jones
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