Re: [PATCH -next v19 05/24] riscv: Clear vector regfile on bootup

Palmer Dabbelt
2023-05-12T00:01:28Z

On Tue, 09 May 2023 03:30:14 PDT (-0700), andy.chiu@sifive.com wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> clear vector registers on boot if kernel supports V.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
> arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 4bf6c449d78b..3fd6a4bd9c3e 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -392,7 +392,7 @@ ENTRY(reset_regs)
> #ifdef CONFIG_FPU
> csrr t0, CSR_MISA
> andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
> - beqz t0, .Lreset_regs_done
> + beqz t0, .Lreset_regs_done_fpu
>
> li t1, SR_FS
> csrs CSR_STATUS, t1
> @@ -430,8 +430,31 @@ ENTRY(reset_regs)
> fmv.s.x f31, zero
> csrw fcsr, 0
> /* note that the caller must clear SR_FS */
> +.Lreset_regs_done_fpu:
> #endif /* CONFIG_FPU */
> -.Lreset_regs_done:
> +
> +#ifdef CONFIG_RISCV_ISA_V
> + csrr t0, CSR_MISA
> + li t1, COMPAT_HWCAP_ISA_V
> + and t0, t0, t1
> + beqz t0, .Lreset_regs_done_vector
> +
> + /*
> + * Clear vector registers and reset vcsr
> + * VLMAX has a defined value, VLEN is a constant,
> + * and this form of vsetvli is defined to set vl to VLMAX.
> + */
> + li t1, SR_VS
> + csrs CSR_STATUS, t1
> + csrs CSR_VCSR, x0
> + vsetvli t1, x0, e8, m8, ta, ma
> + vmv.v.i v0, 0
> + vmv.v.i v8, 0
> + vmv.v.i v16, 0
> + vmv.v.i v24, 0
> + /* note that the caller must clear SR_VS */
> +.Lreset_regs_done_vector:
> +#endif /* CONFIG_RISCV_ISA_V */
> ret
> END(reset_regs)
> #endif /* CONFIG_RISCV_M_MODE */

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>