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From: guoren@kernel.org
To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com,
	tglx@linutronix.de, peterz@infradead.org, luto@kernel.org,
	conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org,
	chenhuacai@kernel.org, apatel@ventanamicro.com,
	atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org,
	paul.walmsley@sifive.com, catalin.marinas@arm.com,
	will@kernel.org, rppt@kernel.org, anup@brainfault.org,
	shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn,
	luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com,
	wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com,
	andy.chiu@sifive.com, vincent.chen@sifive.com,
	greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn,
	jrtc27@jrtc27.com
Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>
Subject: [RFC PATCH 09/22] riscv: s64ilp32: Introduce PTR_L and PTR_S
Date: Thu, 18 May 2023 09:10:00 -0400	[thread overview]
Message-ID: <20230518131013.3366406-10-guoren@kernel.org> (raw)
In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

REG_L and REG_S can't satisfy s64ilp32 situation, because its
__SIZEOF_POINTER__*8 != __riscv_xlen. So we introduce new PTR_L
and PTR_S macro to help head.S and entry.S deal with the pointer
data type and replace all REG_L/S by PTR_L/S to fit the current
algorithm in memcpy, memove, memset, strcmp, strlen and strncmp.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/include/asm/asm.h |  5 +++++
 arch/riscv/kernel/entry.S    | 24 ++++++++++++------------
 arch/riscv/kernel/head.S     |  8 ++++----
 3 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
index 114bbadaef41..1cf20027bdbd 100644
--- a/arch/riscv/include/asm/asm.h
+++ b/arch/riscv/include/asm/asm.h
@@ -38,6 +38,7 @@
 #define RISCV_SZPTR		"8"
 #define RISCV_LGPTR		"3"
 #endif
+#define __PTR_SEL(a, b)		__ASM_STR(a)
 #elif __SIZEOF_POINTER__ == 4
 #ifdef __ASSEMBLY__
 #define RISCV_PTR		.word
@@ -48,10 +49,14 @@
 #define RISCV_SZPTR		"4"
 #define RISCV_LGPTR		"2"
 #endif
+#define __PTR_SEL(a, b)		__ASM_STR(b)
 #else
 #error "Unexpected __SIZEOF_POINTER__"
 #endif
 
+#define PTR_L		__PTR_SEL(ld, lw)
+#define PTR_S		__PTR_SEL(sd, sw)
+
 #if (__SIZEOF_INT__ == 4)
 #define RISCV_INT		__ASM_STR(.word)
 #define RISCV_SZINT		__ASM_STR(4)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 3fbb100bc9e4..9d8a94fec097 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -25,19 +25,19 @@ SYM_CODE_START(handle_exception)
 
 _restore_kernel_tpsp:
 	csrr tp, CSR_SCRATCH
-	REG_S sp, TASK_TI_KERNEL_SP(tp)
+	PTR_S sp, TASK_TI_KERNEL_SP(tp)
 
 #ifdef CONFIG_VMAP_STACK
 	addi sp, sp, -(PT_SIZE_ON_STACK)
 	srli sp, sp, THREAD_SHIFT
 	andi sp, sp, 0x1
 	bnez sp, handle_kernel_stack_overflow
-	REG_L sp, TASK_TI_KERNEL_SP(tp)
+	PTR_L sp, TASK_TI_KERNEL_SP(tp)
 #endif
 
 _save_context:
-	REG_S sp, TASK_TI_USER_SP(tp)
-	REG_L sp, TASK_TI_KERNEL_SP(tp)
+	PTR_S sp, TASK_TI_USER_SP(tp)
+	PTR_L sp, TASK_TI_KERNEL_SP(tp)
 	addi sp, sp, -(PT_SIZE_ON_STACK)
 	REG_S x1,  PT_RA(sp)
 	REG_S x3,  PT_GP(sp)
@@ -53,7 +53,7 @@ _save_context:
 	 */
 	li t0, SR_SUM | SR_FS
 
-	REG_L s0, TASK_TI_USER_SP(tp)
+	PTR_L s0, TASK_TI_USER_SP(tp)
 	csrrc s1, CSR_STATUS, t0
 	csrr s2, CSR_EPC
 	csrr s3, CSR_TVAL
@@ -96,7 +96,7 @@ _save_context:
 	add t0, t1, t0
 	/* Check if exception code lies within bounds */
 	bgeu t0, t2, 1f
-	REG_L t0, 0(t0)
+	PTR_L t0, 0(t0)
 	jr t0
 1:
 	tail do_trap_unknown
@@ -121,7 +121,7 @@ SYM_CODE_START_NOALIGN(ret_from_exception)
 
 	/* Save unwound kernel stack pointer in thread_info */
 	addi s0, sp, PT_SIZE_ON_STACK
-	REG_S s0, TASK_TI_KERNEL_SP(tp)
+	PTR_S s0, TASK_TI_KERNEL_SP(tp)
 
 	/*
 	 * Save TP into the scratch register , so we can find the kernel data
@@ -239,7 +239,7 @@ restore_caller_reg:
 	REG_S x5,  PT_T0(sp)
 	save_from_x6_to_x31
 
-	REG_L s0, TASK_TI_KERNEL_SP(tp)
+	PTR_L s0, TASK_TI_KERNEL_SP(tp)
 	csrr s1, CSR_STATUS
 	csrr s2, CSR_EPC
 	csrr s3, CSR_TVAL
@@ -283,8 +283,8 @@ SYM_FUNC_START(__switch_to)
 	li    a4,  TASK_THREAD_RA
 	add   a3, a0, a4
 	add   a4, a1, a4
-	REG_S ra,  TASK_THREAD_RA_RA(a3)
-	REG_S sp,  TASK_THREAD_SP_RA(a3)
+	PTR_S ra,  TASK_THREAD_RA_RA(a3)
+	PTR_S sp,  TASK_THREAD_SP_RA(a3)
 	REG_S s0,  TASK_THREAD_S0_RA(a3)
 	REG_S s1,  TASK_THREAD_S1_RA(a3)
 	REG_S s2,  TASK_THREAD_S2_RA(a3)
@@ -298,8 +298,8 @@ SYM_FUNC_START(__switch_to)
 	REG_S s10, TASK_THREAD_S10_RA(a3)
 	REG_S s11, TASK_THREAD_S11_RA(a3)
 	/* Restore context from next->thread */
-	REG_L ra,  TASK_THREAD_RA_RA(a4)
-	REG_L sp,  TASK_THREAD_SP_RA(a4)
+	PTR_L ra,  TASK_THREAD_RA_RA(a4)
+	PTR_L sp,  TASK_THREAD_SP_RA(a4)
 	REG_L s0,  TASK_THREAD_S0_RA(a4)
 	REG_L s1,  TASK_THREAD_S1_RA(a4)
 	REG_L s2,  TASK_THREAD_S2_RA(a4)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4bf6c449d78b..27d134ee754f 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -42,7 +42,7 @@ ENTRY(_start)
 	/* Image load offset (0MB) from start of RAM for M-mode */
 	.dword 0
 #else
-#if __riscv_xlen == 64
+#ifdef CONFIG_64BIT
 	/* Image load offset(2MB) from start of RAM */
 	.dword 0x200000
 #else
@@ -75,7 +75,7 @@ relocate_enable_mmu:
 	/* Relocate return address */
 	la a1, kernel_map
 	XIP_FIXUP_OFFSET a1
-	REG_L a1, KERNEL_MAP_VIRT_ADDR(a1)
+	PTR_L a1, KERNEL_MAP_VIRT_ADDR(a1)
 	la a2, _start
 	sub a1, a1, a2
 	add ra, ra, a1
@@ -346,8 +346,8 @@ clear_bss_done:
 	 */
 .Lwait_for_cpu_up:
 	/* FIXME: We should WFI to save some energy here. */
-	REG_L sp, (a1)
-	REG_L tp, (a2)
+	PTR_L sp, (a1)
+	PTR_L tp, (a2)
 	beqz sp, .Lwait_for_cpu_up
 	beqz tp, .Lwait_for_cpu_up
 	fence
-- 
2.36.1


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  parent reply	other threads:[~2023-05-18 13:12 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-18 13:09 [RFC PATCH 00/22] riscv: s64ilp32: Running 32-bit Linux kernel on 64-bit supervisor mode guoren
2023-05-18 13:09 ` [RFC PATCH 01/22] riscv: vdso: Unify vdso32 & compat_vdso into vdso/Makefile guoren
2023-05-18 13:09 ` [RFC PATCH 02/22] riscv: vdso: Remove compat_vdso/ guoren
2023-05-18 13:09 ` [RFC PATCH 03/22] riscv: vdso: Add time-related vDSO common flow for vdso32 guoren
2023-05-18 13:09 ` [RFC PATCH 04/22] clocksource: riscv: s64ilp32: Use __riscv_xlen instead of CONFIG_32BIT guoren
2023-05-18 13:09 ` [RFC PATCH 05/22] riscv: s64ilp32: Introduce xlen_t guoren
2023-05-18 13:09 ` [RFC PATCH 06/22] irqchip: riscv: s64ilp32: Use __riscv_xlen instead of CONFIG_32BIT guoren
2023-05-18 13:09 ` [RFC PATCH 07/22] riscv: s64ilp32: Add sbi support guoren
2023-05-18 13:09 ` [RFC PATCH 08/22] riscv: s64ilp32: Add asid support guoren
2023-05-18 13:10 ` guoren [this message]
2023-05-18 13:10 ` [RFC PATCH 10/22] riscv: s64ilp32: Enable user space runtime environment guoren
2023-05-18 13:10 ` [RFC PATCH 11/22] riscv: s64ilp32: Add ebpf jit support guoren
2023-05-18 13:10 ` [RFC PATCH 12/22] riscv: s64ilp32: Add ELF32 support guoren
2023-05-18 13:10 ` [RFC PATCH 13/22] riscv: s64ilp32: Add ARCH RV64 ILP32 compiling framework guoren
2023-05-18 13:10 ` [RFC PATCH 14/22] riscv: s64ilp32: Add MMU_SV39 mode support for 32BIT guoren
2023-05-18 13:10 ` [RFC PATCH 15/22] riscv: s64ilp32: Enable native atomic64 guoren
2023-05-18 13:10 ` [RFC PATCH 16/22] riscv: s64ilp32: Add TImode (128 int) support guoren
2023-05-18 13:10 ` [RFC PATCH 17/22] riscv: s64ilp32: Implement cmpxchg_double guoren
2023-05-18 13:10 ` [RFC PATCH 18/22] riscv: s64ilp32: Disable KVM guoren
2023-05-18 13:10 ` [RFC PATCH 19/22] riscv: Cleanup rv32_defconfig guoren
2023-05-18 13:10 ` [RFC PATCH 20/22] riscv: s64ilp32: Add rv64ilp32_defconfig guoren
2023-05-18 13:10 ` [RFC PATCH 21/22] riscv: s64ilp32: Correct the rv64ilp32 stackframe layout guoren
2023-05-18 13:10 ` [RFC PATCH 22/22] riscv: s64ilp32: Temporary workaround solution to gcc problem guoren
2023-05-18 15:38 ` [RFC PATCH 00/22] riscv: s64ilp32: Running 32-bit Linux kernel on 64-bit supervisor mode Palmer Dabbelt
2023-05-18 18:29   ` Arnd Bergmann
2023-05-19  0:38     ` Paul Walmsley
2023-05-19  8:55       ` Arnd Bergmann
2023-05-19 15:31     ` Guo Ren
2023-05-19 16:53       ` Arnd Bergmann
2023-05-19 17:18         ` Palmer Dabbelt
2023-05-20  1:43         ` Guo Ren
2023-05-19  0:14   ` Paul Walmsley
2023-05-21 12:37     ` Guo Ren
2023-05-19 20:20 ` Arnd Bergmann
2023-05-20  2:53   ` Guo Ren
2023-05-20 10:13     ` Arnd Bergmann
2023-05-20 15:57       ` Guo Ren

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