From: kernel test robot <lkp@intel.com>
To: Heiko Stuebner <heiko@sntech.de>,
palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: oe-kbuild-all@lists.linux.dev, linux-riscv@lists.infradead.org,
samuel@sholland.org, guoren@kernel.org,
christoph.muellner@vrull.eu, heiko@sntech.de,
conor.dooley@microchip.com, linux-kernel@vger.kernel.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: Re: [PATCH v2 3/3] RISC-V: add T-Head vector errata handling
Date: Fri, 23 Jun 2023 21:47:13 +0800 [thread overview]
Message-ID: <202306232111.5WpYab2n-lkp@intel.com> (raw)
In-Reply-To: <20230622231305.631331-4-heiko@sntech.de>
Hi Heiko,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20230622]
[cannot apply to linus/master v6.4-rc7 v6.4-rc6 v6.4-rc5 v6.4-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Heiko-Stuebner/RISC-V-move-vector-available-status-into-a-dedicated-variable/20230623-081314
base: next-20230622
patch link: https://lore.kernel.org/r/20230622231305.631331-4-heiko%40sntech.de
patch subject: [PATCH v2 3/3] RISC-V: add T-Head vector errata handling
config: riscv-rv32_defconfig (https://download.01.org/0day-ci/archive/20230623/202306232111.5WpYab2n-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230623/202306232111.5WpYab2n-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306232111.5WpYab2n-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/riscv/include/asm/vector.h: Assembler messages:
>> arch/riscv/include/asm/vector.h:162: Error: unrecognized opcode `slliw a4,a4,1'
>> arch/riscv/include/asm/vector.h:194: Error: unrecognized opcode `srliw t4,a1,1'
>> arch/riscv/include/asm/vector.h:169: Error: attempt to move .org backwards
arch/riscv/include/asm/vector.h:203: Error: attempt to move .org backwards
--
arch/riscv/include/asm/vector.h: Assembler messages:
>> arch/riscv/include/asm/vector.h:162: Error: unrecognized opcode `slliw a4,a4,1'
>> arch/riscv/include/asm/vector.h:169: Error: attempt to move .org backwards
--
arch/riscv/include/asm/vector.h: Assembler messages:
>> arch/riscv/include/asm/vector.h:194: Error: unrecognized opcode `srliw t4,a1,1'
>> arch/riscv/include/asm/vector.h:162: Error: unrecognized opcode `slliw a4,a4,1'
arch/riscv/include/asm/vector.h:203: Error: attempt to move .org backwards
>> arch/riscv/include/asm/vector.h:169: Error: attempt to move .org backwards
vim +162 arch/riscv/include/asm/vector.h
03c3fcd9941a17 Greentime Hu 2023-06-05 150
03c3fcd9941a17 Greentime Hu 2023-06-05 151 static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src)
03c3fcd9941a17 Greentime Hu 2023-06-05 152 {
5255e253b722bb Heiko Stuebner 2023-06-23 153 register u32 t1 asm("t1") = (SR_FS);
5255e253b722bb Heiko Stuebner 2023-06-23 154
5255e253b722bb Heiko Stuebner 2023-06-23 155 /*
5255e253b722bb Heiko Stuebner 2023-06-23 156 * Similar to __vstate_csr_save above, restore values for the
5255e253b722bb Heiko Stuebner 2023-06-23 157 * separate VXRM and VXSAT CSRs from the vcsr variable.
5255e253b722bb Heiko Stuebner 2023-06-23 158 */
5255e253b722bb Heiko Stuebner 2023-06-23 159 asm volatile (ALTERNATIVE(
03c3fcd9941a17 Greentime Hu 2023-06-05 160 ".option push\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 161 ".option arch, +v\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 @162 "vsetvl x0, %2, %1\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 163 ".option pop\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 164 "csrw " __stringify(CSR_VSTART) ", %0\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 165 "csrw " __stringify(CSR_VCSR) ", %3\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 166 __nops(6),
5255e253b722bb Heiko Stuebner 2023-06-23 167 "csrs sstatus, t1\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 168 ".option push\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 @169 ".option arch, +v\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 170 "vsetvl x0, %2, %1\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 171 ".option pop\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 172 "csrw " __stringify(CSR_VSTART) ", %0\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 173 "srliw t4, %3, " __stringify(VCSR_VXRM_SHIFT) "\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 174 "andi t4, t4, " __stringify(VCSR_VXRM_MASK) "\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 175 "csrw " __stringify(THEAD_C9XX_CSR_VXRM) ", t4\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 176 "andi %3, %3, " __stringify(VCSR_VXSAT_MASK) "\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 177 "csrw " __stringify(THEAD_C9XX_CSR_VXSAT) ", %3\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 178 "csrc sstatus, t1\n\t",
5255e253b722bb Heiko Stuebner 2023-06-23 179 THEAD_VENDOR_ID,
5255e253b722bb Heiko Stuebner 2023-06-23 180 ERRATA_THEAD_VECTOR, CONFIG_ERRATA_THEAD_VECTOR)
03c3fcd9941a17 Greentime Hu 2023-06-05 181 : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl),
5255e253b722bb Heiko Stuebner 2023-06-23 182 "r" (src->vcsr), "r"(t1) : "t4");
03c3fcd9941a17 Greentime Hu 2023-06-05 183 }
03c3fcd9941a17 Greentime Hu 2023-06-05 184
03c3fcd9941a17 Greentime Hu 2023-06-05 185 static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
03c3fcd9941a17 Greentime Hu 2023-06-05 186 void *datap)
03c3fcd9941a17 Greentime Hu 2023-06-05 187 {
03c3fcd9941a17 Greentime Hu 2023-06-05 188 unsigned long vl;
03c3fcd9941a17 Greentime Hu 2023-06-05 189
03c3fcd9941a17 Greentime Hu 2023-06-05 190 riscv_v_enable();
03c3fcd9941a17 Greentime Hu 2023-06-05 191 __vstate_csr_save(save_to);
5255e253b722bb Heiko Stuebner 2023-06-23 192 asm volatile (ALTERNATIVE(
5255e253b722bb Heiko Stuebner 2023-06-23 193 "nop\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 @194 ".option push\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 195 ".option arch, +v\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 196 "vsetvli %0, x0, e8, m8, ta, ma\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 197 "vse8.v v0, (%1)\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 198 "add %1, %1, %0\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 199 "vse8.v v8, (%1)\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 200 "add %1, %1, %0\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 201 "vse8.v v16, (%1)\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 202 "add %1, %1, %0\n\t"
03c3fcd9941a17 Greentime Hu 2023-06-05 203 "vse8.v v24, (%1)\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 204 ".option pop\n\t",
5255e253b722bb Heiko Stuebner 2023-06-23 205 "mv t0, %1\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 206 THEAD_VSETVLI_T4X0E8M8D1
5255e253b722bb Heiko Stuebner 2023-06-23 207 THEAD_VSB_V_V0T0
5255e253b722bb Heiko Stuebner 2023-06-23 208 "addi t0, t0, 128\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 209 THEAD_VSB_V_V8T0
5255e253b722bb Heiko Stuebner 2023-06-23 210 "addi t0, t0, 128\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 211 THEAD_VSB_V_V16T0
5255e253b722bb Heiko Stuebner 2023-06-23 212 "addi t0, t0, 128\n\t"
5255e253b722bb Heiko Stuebner 2023-06-23 213 THEAD_VSB_V_V24T0, THEAD_VENDOR_ID,
5255e253b722bb Heiko Stuebner 2023-06-23 214 ERRATA_THEAD_VECTOR, CONFIG_ERRATA_THEAD_VECTOR)
5255e253b722bb Heiko Stuebner 2023-06-23 215 : "=&r" (vl) : "r" (datap) : "t0", "t4", "memory");
03c3fcd9941a17 Greentime Hu 2023-06-05 216 riscv_v_disable();
03c3fcd9941a17 Greentime Hu 2023-06-05 217 }
03c3fcd9941a17 Greentime Hu 2023-06-05 218
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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next prev parent reply other threads:[~2023-06-23 13:48 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 23:13 [PATCH v2 0/2] RISC-V: T-Head vector handling Heiko Stuebner
2023-06-22 23:13 ` [PATCH v2 1/3] RISC-V: define the elements of the VCSR vector CSR Heiko Stuebner
2023-06-22 23:13 ` [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable Heiko Stuebner
2023-06-23 9:19 ` Conor Dooley
2023-06-23 13:47 ` kernel test robot
2023-06-22 23:13 ` [PATCH v2 3/3] RISC-V: add T-Head vector errata handling Heiko Stuebner
2023-06-23 3:11 ` kernel test robot
2023-06-23 9:49 ` Conor Dooley
2023-06-23 10:40 ` Heiko Stübner
2023-06-23 11:44 ` Conor Dooley
2023-06-24 5:18 ` Stefan O'Rear
2023-06-24 10:59 ` Andrew Jones
2023-06-28 16:07 ` Andy Chiu
2023-06-23 13:47 ` kernel test robot [this message]
2023-06-27 15:21 ` Rémi Denis-Courmont
2023-06-27 16:12 ` Conor Dooley
2023-06-28 14:23 ` Palmer Dabbelt
2023-06-29 16:06 ` Rémi Denis-Courmont
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