[PATCH] RISC-V: Show accurate per-hart isa in /proc/cpuinfo

From: Evan Green <evan@rivosinc.com>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Evan Green <evan@rivosinc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH] RISC-V: Show accurate per-hart isa in /proc/cpuinfo
Date: Fri, 23 Jun 2023 15:23:53 -0700	[thread overview]
Message-ID: <20230623222353.3742384-1-evan@rivosinc.com> (raw)

In /proc/cpuinfo, most of the information we show for each processor is
specific to that hart: marchid, mvendorid, mimpid, processor, hart,
compatible, and the mmu size. But the ISA string gets filtered through a
lowest common denominator mask, so that if one CPU is missing an ISA
extension, no CPUs will show it.

Now that we track the ISA extensions for each hart, let's report ISA
extension info accurately per-hart in /proc/cpuinfo.

Signed-off-by: Evan Green <evan@rivosinc.com>

---

 arch/riscv/kernel/cpu.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index a2fc952318e9..7bb386f94f01 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -226,7 +226,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
 	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
 };
 
-static void print_isa_ext(struct seq_file *f)
+static void print_isa_ext(struct seq_file *f, unsigned long cpu)
 {
 	struct riscv_isa_ext_data *edata;
 	int i = 0, arr_sz;
@@ -239,7 +239,8 @@ static void print_isa_ext(struct seq_file *f)
 
 	for (i = 0; i <= arr_sz; i++) {
 		edata = &isa_ext_arr[i];
-		if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+		if (!__riscv_isa_extension_available(hart_isa[cpu].isa,
+						     edata->isa_ext_id))
 			continue;
 		seq_printf(f, "_%s", edata->uprop);
 	}
@@ -253,7 +254,7 @@ static void print_isa_ext(struct seq_file *f)
  */
 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
 
-static void print_isa(struct seq_file *f, const char *isa)
+static void print_isa(struct seq_file *f, const char *isa, unsigned long cpu)
 {
 	int i;
 
@@ -261,11 +262,12 @@ static void print_isa(struct seq_file *f, const char *isa)
 	/* Print the rv[64/32] part */
 	seq_write(f, isa, 4);
 	for (i = 0; i < sizeof(base_riscv_exts); i++) {
-		if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
+		if (__riscv_isa_extension_available(hart_isa[cpu].isa,
+						    base_riscv_exts[i] - 'a'))
 			/* Print only enabled the base ISA extensions */
 			seq_write(f, &base_riscv_exts[i], 1);
 	}
-	print_isa_ext(f);
+	print_isa_ext(f, cpu);
 	seq_puts(f, "\n");
 }
 
@@ -324,7 +326,7 @@ static int c_show(struct seq_file *m, void *v)
 	if (acpi_disabled) {
 		node = of_get_cpu_node(cpu_id, NULL);
 		if (!of_property_read_string(node, "riscv,isa", &isa))
-			print_isa(m, isa);
+			print_isa(m, isa, cpu_id);
 
 		print_mmu(m);
 		if (!of_property_read_string(node, "compatible", &compat) &&
@@ -334,7 +336,7 @@ static int c_show(struct seq_file *m, void *v)
 		of_node_put(node);
 	} else {
 		if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))
-			print_isa(m, isa);
+			print_isa(m, isa, cpu_id);
 
 		print_mmu(m);
 	}
-- 
2.34.1


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