From: Andrew Jones <ajones@ventanamicro.com>
To: Stefan O'Rear <sorear@fastmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
paul.walmsley@sifive.com, linux-riscv@lists.infradead.org,
samuel@sholland.org, guoren@kernel.org,
christoph.muellner@vrull.eu, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/3] RISC-V: add T-Head vector errata handling
Date: Sat, 24 Jun 2023 12:59:41 +0200 [thread overview]
Message-ID: <20230624-844c5c4701e8acf9bcf150aa@orel> (raw)
In-Reply-To: <0904a831-82c5-47a0-be55-f1a59d0115c2@app.fastmail.com>
On Sat, Jun 24, 2023 at 01:18:26AM -0400, Stefan O'Rear wrote:
> On Fri, Jun 23, 2023, at 6:40 AM, Heiko Stübner wrote:
...
> >> > +
> >> > +/*
> >> > + * Vector 0.7.1 as used for example on T-Head Xuantie cores, uses an older
> >> > + * encoding for vsetvli (ta, ma vs. d1), so provide an instruction for
> >> > + * vsetvli t4, x0, e8, m8, d1
> >> > + */
> >> > +#define THEAD_VSETVLI_T4X0E8M8D1 ".long 0x00307ed7\n\t"
> >> > +
> >> > +/*
> >> > + * While in theory, the vector-0.7.1 vsb.v and vlb.v result in the same
> >> > + * encoding as the standard vse8.v and vle8.v, compilers seem to optimize
> >> > + * the call resulting in a different encoding and then using a value for
> >> > + * the "mop" field that is not part of vector-0.7.1
> >> > + * So encode specific variants for vstate_save and _restore.
> >> > + */
> >> > +#define THEAD_VSB_V_V0T0 ".long 0x02028027\n\t"
> >> > +#define THEAD_VSB_V_V8T0 ".long 0x02028427\n\t"
> >> > +#define THEAD_VSB_V_V16T0 ".long 0x02028827\n\t"
> >> > +#define THEAD_VSB_V_V24T0 ".long 0x02028c27\n\t"
> >> > +#define THEAD_VLB_V_V0T0 ".long 0x012028007\n\t"
> >> > +#define THEAD_VLB_V_V8T0 ".long 0x012028407\n\t"
> >> > +#define THEAD_VLB_V_V16T0 ".long 0x012028807\n\t"
> >> > +#define THEAD_VLB_V_V24T0 ".long 0x012028c07\n\t"
>
> .insn isn't supported by the kernel's minimum binutils version, but it _is_
> supported by the oldest version of binutils that can assemble rvv 1.0
> instructions. OP_V requires 2.39 so I use a literal 0x57 instead.
>
> very untested, and I leave it to your judgement whether it actually improves
> readability:
>
> #define THEAD_VSETVLI_T4X0E8M8D1 ".insn i 0x57, 7, t4, x0, 3\n\t"
> #define THEAD_VSB_V_V0T0 ".insn r STORE_FP, 0, 1, x0, t0, x0\n\t"
> #define THEAD_VSB_V_V8T0 ".insn r STORE_FP, 0, 1, x8, t0, x0\n\t"
> #define THEAD_VSB_V_V16T0 ".insn r STORE_FP, 0, 1, x16, t0, x0\n\t"
> #define THEAD_VSB_V_V24T0 ".insn r STORE_FP, 0, 1, x24, t0, x0\n\t"
> #define THEAD_VSB_V_V0T0 ".insn r LOAD_FP, 0, 9, x0, t0, x0\n\t"
> #define THEAD_VSB_V_V8T0 ".insn r LOAD_FP, 0, 9, x8, t0, x0\n\t"
> #define THEAD_VSB_V_V16T0 ".insn r LOAD_FP, 0, 9, x16, t0, x0\n\t"
> #define THEAD_VSB_V_V24T0 ".insn r LOAD_FP, 0, 9, x24, t0, x0\n\t"
>
We have the INSN_R() macro in arch/riscv/include/asm/insn-def.h for stuff
like this.
Thanks,
drew
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next prev parent reply other threads:[~2023-06-24 11:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 23:13 [PATCH v2 0/2] RISC-V: T-Head vector handling Heiko Stuebner
2023-06-22 23:13 ` [PATCH v2 1/3] RISC-V: define the elements of the VCSR vector CSR Heiko Stuebner
2023-06-22 23:13 ` [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable Heiko Stuebner
2023-06-23 9:19 ` Conor Dooley
2023-06-23 13:47 ` kernel test robot
2023-06-22 23:13 ` [PATCH v2 3/3] RISC-V: add T-Head vector errata handling Heiko Stuebner
2023-06-23 3:11 ` kernel test robot
2023-06-23 9:49 ` Conor Dooley
2023-06-23 10:40 ` Heiko Stübner
2023-06-23 11:44 ` Conor Dooley
2023-06-24 5:18 ` Stefan O'Rear
2023-06-24 10:59 ` Andrew Jones [this message]
2023-06-28 16:07 ` Andy Chiu
2023-06-23 13:47 ` kernel test robot
2023-06-27 15:21 ` Rémi Denis-Courmont
2023-06-27 16:12 ` Conor Dooley
2023-06-28 14:23 ` Palmer Dabbelt
2023-06-29 16:06 ` Rémi Denis-Courmont
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