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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id jz3-20020a170906bb0300b009829d2e892csm775425ejb.15.2023.06.24.03.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Jun 2023 03:59:42 -0700 (PDT) Date: Sat, 24 Jun 2023 12:59:41 +0200 From: Andrew Jones To: Stefan O'Rear Cc: Heiko Stuebner , Conor Dooley , Palmer Dabbelt , paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, samuel@sholland.org, guoren@kernel.org, christoph.muellner@vrull.eu, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/3] RISC-V: add T-Head vector errata handling Message-ID: <20230624-844c5c4701e8acf9bcf150aa@orel> References: <20230622231305.631331-1-heiko@sntech.de> <20230622231305.631331-4-heiko@sntech.de> <20230623-excluding-sprint-aea9cca0cb02@wendy> <1908808.taCxCBeP46@diego> <0904a831-82c5-47a0-be55-f1a59d0115c2@app.fastmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <0904a831-82c5-47a0-be55-f1a59d0115c2@app.fastmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230624_035945_950979_A9DDBA2A X-CRM114-Status: GOOD ( 17.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, Jun 24, 2023 at 01:18:26AM -0400, Stefan O'Rear wrote: > On Fri, Jun 23, 2023, at 6:40 AM, Heiko St=FCbner wrote: ... > >> > + > >> > +/* > >> > + * Vector 0.7.1 as used for example on T-Head Xuantie cores, uses a= n older > >> > + * encoding for vsetvli (ta, ma vs. d1), so provide an instruction = for > >> > + * vsetvli t4, x0, e8, m8, d1 > >> > + */ > >> > +#define THEAD_VSETVLI_T4X0E8M8D1 ".long 0x00307ed7\n\t" > >> > + > >> > +/* > >> > + * While in theory, the vector-0.7.1 vsb.v and vlb.v result in the = same > >> > + * encoding as the standard vse8.v and vle8.v, compilers seem to op= timize > >> > + * the call resulting in a different encoding and then using a valu= e for > >> > + * the "mop" field that is not part of vector-0.7.1 > >> > + * So encode specific variants for vstate_save and _restore. > >> > + */ > >> > +#define THEAD_VSB_V_V0T0 ".long 0x02028027\n\t" > >> > +#define THEAD_VSB_V_V8T0 ".long 0x02028427\n\t" > >> > +#define THEAD_VSB_V_V16T0 ".long 0x02028827\n\t" > >> > +#define THEAD_VSB_V_V24T0 ".long 0x02028c27\n\t" > >> > +#define THEAD_VLB_V_V0T0 ".long 0x012028007\n\t" > >> > +#define THEAD_VLB_V_V8T0 ".long 0x012028407\n\t" > >> > +#define THEAD_VLB_V_V16T0 ".long 0x012028807\n\t" > >> > +#define THEAD_VLB_V_V24T0 ".long 0x012028c07\n\t" > = > .insn isn't supported by the kernel's minimum binutils version, but it _i= s_ > supported by the oldest version of binutils that can assemble rvv 1.0 > instructions. OP_V requires 2.39 so I use a literal 0x57 instead. > = > very untested, and I leave it to your judgement whether it actually impro= ves > readability: > = > #define THEAD_VSETVLI_T4X0E8M8D1 ".insn i 0x57, 7, t4, x0, 3\n\t" > #define THEAD_VSB_V_V0T0 ".insn r STORE_FP, 0, 1, x0, t0, x0\n\t" > #define THEAD_VSB_V_V8T0 ".insn r STORE_FP, 0, 1, x8, t0, x0\n\t" > #define THEAD_VSB_V_V16T0 ".insn r STORE_FP, 0, 1, x16, t0, x0\n\t" > #define THEAD_VSB_V_V24T0 ".insn r STORE_FP, 0, 1, x24, t0, x0\n\t" > #define THEAD_VSB_V_V0T0 ".insn r LOAD_FP, 0, 9, x0, t0, x0\n\t" > #define THEAD_VSB_V_V8T0 ".insn r LOAD_FP, 0, 9, x8, t0, x0\n\t" > #define THEAD_VSB_V_V16T0 ".insn r LOAD_FP, 0, 9, x16, t0, x0\n\t" > #define THEAD_VSB_V_V24T0 ".insn r LOAD_FP, 0, 9, x24, t0, x0\n\t" > We have the INSN_R() macro in arch/riscv/include/asm/insn-def.h for stuff like this. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv