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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id z18-20020aa7c652000000b0050dfd7de30dsm2904899edr.94.2023.06.26.08.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jun 2023 08:14:16 -0700 (PDT) Date: Mon, 26 Jun 2023 17:14:15 +0200 From: Andrew Jones To: Conor Dooley Subject: Re: [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Message-ID: <20230626-e3ea7beb39c584bfbf7ee836@orel> References: <20230626-provable-angrily-81760e8c3cc6@wendy> <20230626-silk-colonize-824390303994@wendy> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230626-silk-colonize-824390303994@wendy> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230626_081425_043935_6DEBA28B X-CRM114-Status: GOOD ( 24.44 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Albert Ou , linux-kernel@vger.kernel.org, conor@kernel.org, Rob Herring , palmer@dabbelt.com, Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Heiko Stuebner , Evan Green Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 26, 2023 at 12:19:39PM +0100, Conor Dooley wrote: > From: Heiko Stuebner > > When filling hwcap the kernel already expects the isa string to start with > rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT. > > So when recreating the runtime isa-string we can also just go the other way > to get the correct starting point for it. > > Signed-off-by: Heiko Stuebner > Co-developed-by: Conor Dooley > Signed-off-by: Conor Dooley > --- > arch/riscv/kernel/cpu.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index a2fc952318e9..742bb42e7e86 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -253,13 +253,16 @@ static void print_isa_ext(struct seq_file *f) > */ > static const char base_riscv_exts[13] = "imafdqcbkjpvh"; > > -static void print_isa(struct seq_file *f, const char *isa) > +static void print_isa(struct seq_file *f) > { > int i; > > seq_puts(f, "isa\t\t: "); > - /* Print the rv[64/32] part */ > - seq_write(f, isa, 4); > + if (IS_ENABLED(CONFIG_32BIT)) > + seq_write(f, "rv32", 4); > + else > + seq_write(f, "rv64", 4); > + > for (i = 0; i < sizeof(base_riscv_exts); i++) { > if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) > /* Print only enabled the base ISA extensions */ > @@ -316,15 +319,14 @@ static int c_show(struct seq_file *m, void *v) > unsigned long cpu_id = (unsigned long)v - 1; > struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); > struct device_node *node; > - const char *compat, *isa; > + const char *compat; > > seq_printf(m, "processor\t: %lu\n", cpu_id); > seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); > + print_isa(m); > > if (acpi_disabled) { > node = of_get_cpu_node(cpu_id, NULL); > - if (!of_property_read_string(node, "riscv,isa", &isa)) > - print_isa(m, isa); > > print_mmu(m); > if (!of_property_read_string(node, "compatible", &compat) && > @@ -333,8 +335,6 @@ static int c_show(struct seq_file *m, void *v) > > of_node_put(node); > } else { > - if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) > - print_isa(m, isa); > Extra blank line here to remove. Actually the whole 'else' can be removed because the print_mmu() call can be brought up above the 'if (acpi_disabled)' > print_mmu(m); > } > -- > 2.40.1 > Otherwise, Reviewed-by: Andrew Jones Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv