From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, conor@kernel.org,
conor.dooley@microchip.com, Rob Herring <robh+dt@kernel.org>,
Evan Green <evan@rivosinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v1 5/9] RISC-V: add missing single letter extension definitions
Date: Mon, 26 Jun 2023 12:19:43 +0100 [thread overview]
Message-ID: <20230626-possible-poet-ae4afce0a525@wendy> (raw)
In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy>
To facilitate adding single letter extensions to riscv_isa_ext, add
definitions for the extensions present in base_riscv_exts that do not
already have them.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/hwcap.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 36f46dfd2b87..a35bee219dd7 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -14,12 +14,17 @@
#include <uapi/asm/hwcap.h>
#define RISCV_ISA_EXT_a ('a' - 'a')
+#define RISCV_ISA_EXT_b ('b' - 'a')
#define RISCV_ISA_EXT_c ('c' - 'a')
#define RISCV_ISA_EXT_d ('d' - 'a')
#define RISCV_ISA_EXT_f ('f' - 'a')
#define RISCV_ISA_EXT_h ('h' - 'a')
#define RISCV_ISA_EXT_i ('i' - 'a')
+#define RISCV_ISA_EXT_j ('j' - 'a')
+#define RISCV_ISA_EXT_k ('k' - 'a')
#define RISCV_ISA_EXT_m ('m' - 'a')
+#define RISCV_ISA_EXT_p ('p' - 'a')
+#define RISCV_ISA_EXT_q ('q' - 'a')
#define RISCV_ISA_EXT_s ('s' - 'a')
#define RISCV_ISA_EXT_u ('u' - 'a')
#define RISCV_ISA_EXT_v ('v' - 'a')
--
2.40.1
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next prev parent reply other threads:[~2023-06-26 11:21 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-26 11:19 [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-26 15:14 ` Andrew Jones
2023-06-26 15:51 ` Conor Dooley
2023-06-26 16:05 ` Andrew Jones
2023-06-26 16:16 ` Conor Dooley
2023-06-27 8:02 ` Sunil V L
2023-06-27 8:51 ` Conor Dooley
2023-06-27 9:20 ` Sunil V L
2023-06-26 11:19 ` [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-06-26 15:19 ` Andrew Jones
2023-06-26 16:08 ` Conor Dooley
2023-06-26 16:29 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-26 15:29 ` Andrew Jones
2023-06-26 15:44 ` Andrew Jones
2023-06-26 15:59 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-26 15:33 ` Andrew Jones
2023-06-26 11:19 ` Conor Dooley [this message]
2023-06-26 15:34 ` [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Andrew Jones
2023-06-26 11:19 ` [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-26 15:42 ` Andrew Jones
2023-06-28 17:33 ` Evan Green
2023-06-28 17:43 ` Conor Dooley
2023-06-28 17:50 ` Evan Green
2023-06-26 11:19 ` [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-26 16:17 ` Andrew Jones
2023-06-27 17:42 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 8/9] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-26 16:24 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-26 16:25 ` Andrew Jones
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