From: Conor Dooley <conor@kernel.org>
To: Samuel Ortiz <sameo@rivosinc.com>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, linux@rivosinc.com,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
"Anup Patel" <apatel@ventanamicro.com>,
linux-kernel@vger.kernel.org,
"Hongren (Zenithal) Zheng" <i@zenithal.me>,
"Guo Ren" <guoren@kernel.org>,
"Atish Patra" <atishp@rivosinc.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Evan Green" <evan@rivosinc.com>
Subject: Re: [PATCH 3/3] RISC-V: Implement archrandom when Zkr is available
Date: Tue, 27 Jun 2023 20:09:08 +0100 [thread overview]
Message-ID: <20230627-grinning-droop-bfbb327f6164@spud> (raw)
In-Reply-To: <20230627143747.1599218-4-sameo@rivosinc.com>
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Hey Samuel,
On Tue, Jun 27, 2023 at 04:37:44PM +0200, Samuel Ortiz wrote:
> The Zkr extension is ratified and provides 16 bits of entropy seed when
> reading the SEED CSR.
>
> We can implement arch_get_random_seed_longs() by doing multiple csrrw to
> that CSR and filling an unsigned long with valid entropy bits.
>
> Signed-off-by: Samuel Ortiz <sameo@rivosinc.com>
> ---
> arch/riscv/include/asm/archrandom.h | 66 +++++++++++++++++++++++++++++
> arch/riscv/include/asm/csr.h | 9 ++++
> 2 files changed, 75 insertions(+)
> create mode 100644 arch/riscv/include/asm/archrandom.h
>
> diff --git a/arch/riscv/include/asm/archrandom.h b/arch/riscv/include/asm/archrandom.h
> new file mode 100644
> index 000000000000..3d01aab2800a
> --- /dev/null
> +++ b/arch/riscv/include/asm/archrandom.h
> @@ -0,0 +1,66 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Kernel interface for the RISCV arch_random_* functions
> + *
> + * Copyright (c) 2022 by Rivos Inc.
> + *
> + */
> +
> +#ifndef ASM_RISCV_ARCHRANDOM_H
> +#define ASM_RISCV_ARCHRANDOM_H
> +
> +#include <asm/csr.h>
> +
> +#define PR_PREFIX "Zkr Extension: "
Does pr_fmt() not work for you?
Also, "Zkr Extension" doesn't really seem super helpful to a punter if
they saw it in a log. Why not s/Zkr Extension/archrandom/, or similar?
> +#define SEED_RETRY_LOOPS 10
> +
> +static inline bool __must_check csr_seed_long(unsigned long *v)
> +{
> + unsigned int retry = SEED_RETRY_LOOPS;
> + unsigned int needed_seeds = sizeof(unsigned long) / 2, valid_seeds = 0;
> + u16 *entropy = (u16 *)v;
> +
> + do {
> + /*
> + * The SEED CSR (0x015) must be accessed with a read-write
> + * instruction. Moreover, implementations must ignore the write
> + * value, its purpose is to signal polling for new seed.
> + */
What relevance does the second half of this comment have to the kernel?
> + unsigned long csr_seed = csr_swap(CSR_SEED, 0);
> +
> + switch (csr_seed & SEED_OPST_MASK) {
> + case SEED_OPST_ES16:
> + entropy[valid_seeds++] = csr_seed & SEED_ENTROPY_MASK;
> + if (valid_seeds == needed_seeds)
> + return true;
> + break;
> +
> + case SEED_OPST_DEAD:
> + pr_err_once(PR_PREFIX "Unrecoverable error\n");
> + return false;
> +
> + case SEED_OPST_BIST:
> + pr_info(PR_PREFIX "On going Built-in Self Test\n");
tiny nit, "On-going"? My OCD is bother by the capitalisation otherwise.
> + fallthrough;
> +
> + case SEED_OPST_WAIT:
> + default:
> + continue;
> + }
> +
> + } while (--retry);
> +
> + return false;
> +}
> +
> +static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
> +{
> + return 0;
> +}
> +
> +static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
> +{
> + return max_longs && riscv_isa_extension_available(NULL, ZKR) && csr_seed_long(v) ? 1 : 0;
Could you please write this in a more readable way, even if that is
going to be a lot more verbose? I know you copied it from x86, but
that's not really an excuse ;)
Also, is there a reason that you opted not to use the alternative-backed
riscv_has_extension_[un]likely() here? The ones backed by alternatives
are preferred if you are not checking on a per-cpu, or once-off basis.
Cheers,
Conor.
> +}
> +
> +#endif /* ASM_RISCV_ARCHRANDOM_H */
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index b98b3b6c9da2..7d0ca9082c66 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -389,6 +389,15 @@
> #define CSR_VTYPE 0xc21
> #define CSR_VLENB 0xc22
>
> +/* Scalar Crypto Extension - Entropy */
> +#define CSR_SEED 0x015
> +#define SEED_OPST_MASK _AC(0xC0000000, UL)
> +#define SEED_OPST_BIST _AC(0x00000000, UL)
> +#define SEED_OPST_WAIT _AC(0x40000000, UL)
> +#define SEED_OPST_ES16 _AC(0x80000000, UL)
> +#define SEED_OPST_DEAD _AC(0xC0000000, UL)
> +#define SEED_ENTROPY_MASK _AC(0xFFFF, UL)
> +
> #ifdef CONFIG_RISCV_M_MODE
> # define CSR_STATUS CSR_MSTATUS
> # define CSR_IE CSR_MIE
> --
> 2.41.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2023-06-27 19:09 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-27 14:37 [PATCH 0/3] RISC-V: archrandom support Samuel Ortiz
2023-06-27 14:37 ` [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT Samuel Ortiz
2023-06-27 18:14 ` Evan Green
2023-06-27 18:44 ` Hongren (Zenithal) Zheng
2023-06-27 18:48 ` Conor Dooley
2023-06-27 19:03 ` Hongren (Zenithal) Zheng
2023-06-27 19:18 ` Conor Dooley
2023-06-28 9:59 ` Samuel Ortiz
2023-06-28 10:01 ` Samuel Ortiz
2023-06-28 11:10 ` Conor Dooley
2023-06-28 12:30 ` Samuel Ortiz
2023-06-28 16:49 ` Conor Dooley
2023-06-28 17:18 ` Evan Green
2023-06-28 17:24 ` Conor Dooley
2023-07-03 17:39 ` Conor Dooley
2023-06-28 11:21 ` Markus Elfring
2023-06-28 12:29 ` Samuel Ortiz
2023-06-27 14:37 ` [PATCH 2/3] RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions Samuel Ortiz
2023-06-27 18:13 ` Evan Green
2023-06-28 0:34 ` Stefan O'Rear
2023-06-28 10:04 ` Samuel Ortiz
2023-06-28 13:25 ` Stefan O'Rear
2023-07-10 7:59 ` Samuel Ortiz
2023-07-12 5:54 ` Stefan O'Rear
2023-06-27 14:37 ` [PATCH 3/3] RISC-V: Implement archrandom when Zkr is available Samuel Ortiz
2023-06-27 19:09 ` Conor Dooley [this message]
2023-06-28 12:28 ` Samuel Ortiz
2023-06-28 1:00 ` Stefan O'Rear
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