From: Conor Dooley <conor.dooley@microchip.com>
To: Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: Conor Dooley <conor@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v5 2/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Thu, 29 Jun 2023 10:01:07 +0100 [thread overview]
Message-ID: <20230629-throng-creation-a33bbd191c1a@wendy> (raw)
In-Reply-To: <2270fd7f-1751-066a-0da5-e35cdd59fd2f@starfivetech.com>
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On Thu, Jun 29, 2023 at 02:42:39PM +0800, Xingyu Wu wrote:
> On 2023/6/29 1:34, Conor Dooley wrote:
> > On Wed, Jun 28, 2023 at 02:44:10PM +0800, Xingyu Wu wrote:
> >> On 2023/6/14 2:31, Krzysztof Kozlowski wrote:
> >> > On 13/06/2023 14:58, Xingyu Wu wrote:
> >> >> From: William Qiu <william.qiu@starfivetech.com>
> >> >> +allOf:
> >> >> + - if:
> >> >> + properties:
> >> >> + compatible:
> >> >> + contains:
> >> >> + const: starfive,jh7110-aon-syscon
> >> >> + then:
> >> >> + required:
> >> >> + - "#power-domain-cells"
> >> >
> >> > Where did you implement the results of the discussion that only some
> >> > devices can have power and clock controller?
> >> >
> >> > According to your code all of above - sys, aon and stg - have clock and
> >> > power controllers. If not, then the code is not correct, so please do
> >> > not respond with what is where (like you did last time) but actually
> >> > implement what you say.
> Yeah, following your advice, I modified the codes and there are two options:
>
> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -41,6 +41,16 @@ required:
> - reg
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-sys-syscon
> + then:
> + required:
> + - clock-controller
> + properties:
> + "#power-domain-cells": false
> - if:
> properties:
> compatible:
> contains:
> const: starfive,jh7110-aon-syscon
> then:
> required:
> - "#power-domain-cells"
> + properties:
> + clock-controller: false
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-stg-syscon
> + then:
> + properties:
> + clock-controller: false
> + "#power-domain-cells": false
>
> additionalProperties: false
>
> Or :
>
> --- a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -41,6 +41,17 @@ required:
> - reg
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: starfive,jh7110-sys-syscon
> + then:
> + required:
> + - clock-controller
> + else:
> + properties:
> + clock-controller: false
> - if:
> properties:
> compatible:
> contains:
> const: starfive,jh7110-aon-syscon
> then:
> required:
> - "#power-domain-cells"
> + else:
> + properties:
> + "#power-domain-cells": false
>
> additionalProperties: false
>
> Which one is better? Thanks.
This second one looks better to me, as it achieves the same thing in a
simpler way.
Cheers,
Conor.
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next prev parent reply other threads:[~2023-06-29 9:01 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 12:58 [PATCH v5 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-06-13 19:06 ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-06-13 18:31 ` Krzysztof Kozlowski
2023-06-28 6:44 ` Xingyu Wu
2023-06-28 17:34 ` Conor Dooley
2023-06-29 6:42 ` Xingyu Wu
2023-06-29 9:01 ` Conor Dooley [this message]
2023-06-13 18:32 ` Krzysztof Kozlowski
2023-06-13 12:58 ` [PATCH v5 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-06-13 18:34 ` Krzysztof Kozlowski
2023-06-13 19:17 ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-06-13 12:58 ` [PATCH v5 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-06-13 19:58 ` Conor Dooley
2023-06-13 12:58 ` [PATCH v5 7/7] riscv: dts: starfive: jh7110: Add PLL clock source in SYSCRG node Xingyu Wu
2023-06-13 19:55 ` Conor Dooley
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