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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id k26-20020a17090627da00b00992e94bcfabsm460906ejc.167.2023.06.30.03.35.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 03:35:04 -0700 (PDT) Date: Fri, 30 Jun 2023 12:35:03 +0200 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 03/10] riscv: Make legacy counter enum match the HW numbering Message-ID: <20230630-ba45f06f3d9faba17c6d8f6a@orel> References: <20230630083013.102334-1-alexghiti@rivosinc.com> <20230630083013.102334-4-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230630083013.102334-4-alexghiti@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230630_033508_295141_DEA333AD X-CRM114-Status: GOOD ( 18.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jun 30, 2023 at 10:30:06AM +0200, Alexandre Ghiti wrote: > RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this > hardware counter from CSR_CYCLE is actually 2: make this offset match the > real hw offset so that we can directly expose those values to userspace. > > Signed-off-by: Alexandre Ghiti > --- > drivers/perf/riscv_pmu_legacy.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c > index ca9e20bfc7ac..6a000abc28bb 100644 > --- a/drivers/perf/riscv_pmu_legacy.c > +++ b/drivers/perf/riscv_pmu_legacy.c > @@ -13,7 +13,7 @@ > #include > > #define RISCV_PMU_LEGACY_CYCLE 0 > -#define RISCV_PMU_LEGACY_INSTRET 1 > +#define RISCV_PMU_LEGACY_INSTRET 2 > > static bool pmu_init_done; > > -- > 2.39.2 > Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv