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From: Conor Dooley <conor@kernel.org>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: linux-acpi@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
Date: Wed, 12 Jul 2023 18:13:38 +0100	[thread overview]
Message-ID: <20230712-quickness-viscosity-ca1a15ccdfcb@spud> (raw)
In-Reply-To: <mhng-c30cb4e2-0574-4051-b220-01601d9579de@palmer-ri-x1c9a>


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On Wed, Jul 12, 2023 at 10:05:39AM -0700, Palmer Dabbelt wrote:
> On Tue, 11 Jul 2023 15:52:56 PDT (-0700), Conor Dooley wrote:

> > Although my rationale was that if we get as far as here, then Zicsr and
> > Zifencei are going to be enabled anyway so there is no harm in setting
> > it for both. I probably should have been less of a cute hoor though.
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> I think there's no way to get here without the extensions, not 100% sure
> though.  I'm mainly trying to avoid going down the same rabbit hole of ISA
> string compatibility hacks in ACPI that we have for DT, though -- I'm sure
> we'll end up with a mess as soon as we release, but might as well catch as
> much as we can.

Seems reasonable to me chief :+1:

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  reply	other threads:[~2023-07-12 17:13 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-11 22:46 [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI Palmer Dabbelt
2023-07-11 22:52 ` Conor Dooley
2023-07-12 17:05   ` Palmer Dabbelt
2023-07-12 17:13     ` Conor Dooley [this message]
2023-07-12  6:42 ` Sunil V L
2023-07-13 23:50 ` patchwork-bot+linux-riscv

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