Re: [PATCH v2] RISC-V: Don't trust V from the riscv,isa DT property on T-Head CPUs

[Conor Dooley <conor@kernel.org>]

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On Fri, Jul 14, 2023 at 12:10:24PM +0100, Conor Dooley wrote:
> On Fri, Jul 14, 2023 at 02:14:45PM +0800, Guo Ren wrote:
> > On Fri, Jul 14, 2023 at 1:45 AM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Thu, Jul 13, 2023 at 01:33:56PM -0400, Guo Ren wrote:
> > > > On Thu, Jul 13, 2023 at 12:48 PM Jisheng Zhang <jszhang@kernel.org> wrote:
> > > > > On Wed, Jul 12, 2023 at 06:48:02PM +0100, Conor Dooley wrote:
> > >
> > > > > > +             /*
> > > > > > +              * "V" in ISA strings is ambiguous in practice: it should mean
> > > > > > +              * just the standard V-1.0 but vendors aren't well behaved.
> > > > > > +              * Many vendors with T-Head CPU cores which implement the 0.7.1
> > > > > > +              * version of the vector specification put "v" into their DTs
> > > > > > +              * and no T-Head CPU cores with the standard version of vector
> > > > > > +              * are in circulation yet.
> > >
> > > > T-HEAD's vector 1.0 SoCs is in circulation. Kendryte K230 is the
> > > > shipped SoC chip, which vendor id = THEAD_VENDOR_ID and with vector
> > > > 1.0.
> > >
> > > Where can I buy one, if it is in circulation?
> > > Googling in English might not be the best thing to do, but doing so I
> > > could find basically no information on the k230 - I did know it existed
> > > and tried to find some info on it before sending the patch.
> > > If it is not in circulation, then the comment is not inaccurate & when
> > > they do arrive they can use the new dedicated property to convey support
> > > for vector.
> 
> I saw you sent to Palmer a link to the k230. When I clicked the link,
> it gave (per google translate) purchase options for k210 and k510 only.
> I figure that means there is nothing _publicly_ available?
> 
> > > > > > +              * Platforms with T-Head CPU cores that support the standard
> > > > > > +              * version of vector must provide the explicit V property,
> > > > > > +              * which is well defined.
> > > > > > +              */
> > > > > > +             if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID) {
> > > > If you insist on doing this, please:
> > > >
> > > > if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID &&
> > > > riscv_cached_marchid(cpu) == 0 && riscv_cached_mimpid(cpu) == 0) {
> > >
> > > Why? Does the c908 report non-zero mimpid/marchid?
> 
> > Yes
> 
> > > If yes, does it need either the errata for CMOs or the page tables?
> 
> > C908 is compatible to RVA22 Profile, here is the detail link:
> > https://xrvm.com/cpu-details?id=4107904466789928960
> 
> That's fantastic news! I'll submit a v3 of this with the hammer reduced,
> as you have suggested above.

From some chat on IRC, I realised that this xrvm.com link mentions that
the c908 supports both XMAE and Svpbmt.
If it does support both, could you explain about how that works?
Is there some CSR that allows to switch between them?
How do you intend communicating to s-mode etc which of them is in use?

Thanks,
Conor.

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