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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id o20-20020a5d58d4000000b0031433443265sm3618211wrf.53.2023.07.21.02.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 02:13:10 -0700 (PDT) Date: Fri, 21 Jul 2023 11:13:09 +0200 From: Andrew Jones To: Mayuresh Chitale Cc: Palmer Dabbelt , Anup Patel , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v2 6/6] RISCV: KVM: Add sstateen0 to ONE_REG Message-ID: <20230721-9b2298b97fbc5223d1487202@orel> References: <20230721075439.454473-1-mchitale@ventanamicro.com> <20230721075439.454473-7-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230721075439.454473-7-mchitale@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_021315_146250_20C975F5 X-CRM114-Status: GOOD ( 21.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jul 21, 2023 at 01:24:39PM +0530, Mayuresh Chitale wrote: > Add support for sstateen0 CSR to the ONE_REG interface to allow its > access from user space. > > Signed-off-by: Mayuresh Chitale > --- > arch/riscv/include/uapi/asm/kvm.h | 9 +++++++ > arch/riscv/kvm/vcpu.c | 40 +++++++++++++++++++++++++++++++ > 2 files changed, 49 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index 74c7f42de29d..bdddfb20299a 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -93,6 +93,11 @@ struct kvm_riscv_aia_csr { > unsigned long iprio2h; > }; > > +/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ > +struct kvm_riscv_smstateen_csr { > + unsigned long sstateen0; > +}; > + > /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ > struct kvm_riscv_timer { > __u64 frequency; > @@ -173,10 +178,14 @@ enum KVM_RISCV_SBI_EXT_ID { > #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) > #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) > #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) > +#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) > + > #define KVM_REG_RISCV_CSR_REG(name) \ > (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) > #define KVM_REG_RISCV_CSR_AIA_REG(name) \ > (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) > +#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ > + (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) > > /* Timer registers are mapped as type 4 */ > #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index ae750decbefe..af7549374c4b 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -507,6 +507,34 @@ static int kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu, > return 0; > } > > +static inline int kvm_riscv_vcpu_smstateen_set_csr(struct kvm_vcpu *vcpu, > + unsigned long reg_num, > + unsigned long reg_val) > +{ > + struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; > + > + if (reg_num >= sizeof(struct kvm_riscv_smstateen_csr) / > + sizeof(unsigned long)) > + return -EINVAL; > + > + ((unsigned long *)csr)[reg_num] = reg_val; > + return 0; > +} > + > +static int kvm_riscv_vcpu_smstateen_get_csr(struct kvm_vcpu *vcpu, > + unsigned long reg_num, > + unsigned long *out_val) > +{ > + struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; > + > + if (reg_num >= sizeof(struct kvm_riscv_smstateen_csr) / > + sizeof(unsigned long)) > + return -EINVAL; > + > + *out_val = ((unsigned long *)csr)[reg_num]; > + return 0; > +} > + > static inline int kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu, > unsigned long reg_num, > unsigned long reg_val) > @@ -552,6 +580,12 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, > case KVM_REG_RISCV_CSR_AIA: > rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, ®_val); > break; > + case KVM_REG_RISCV_CSR_SMSTATEEN: > + rc = -EINVAL; > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) > + rc = kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num, > + ®_val); > + break; > default: > rc = -EINVAL; > break; > @@ -591,6 +625,12 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, > case KVM_REG_RISCV_CSR_AIA: > rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val); > break; > + case KVM_REG_RISCV_CSR_SMSTATEEN: > + rc = -EINVAL; > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) > + rc = kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num, > + reg_val); > + break; > default: > rc = -EINVAL; > break; > -- > 2.34.1 > The EINVAL's will get changed to ENOENT's with the get/set-one-reg error code rework that's coming after get-reg-list lands, but for now I guess it makes sense to leave them consistent with the others. Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv