From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: Re: [PATCH v2 1/6] RISC-V: Detect Smstateen extension
Date: Fri, 21 Jul 2023 10:07:37 +0100 [thread overview]
Message-ID: <20230721-gravy-sturdy-1555d952cfb9@spud> (raw)
In-Reply-To: <20230721-72554b5197954b80af35a7bb@orel>
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Hey,
On Fri, Jul 21, 2023 at 10:49:54AM +0200, Andrew Jones wrote:
> On Fri, Jul 21, 2023 at 01:24:34PM +0530, Mayuresh Chitale wrote:
> > Extend the ISA string parsing to detect the Smstateen extension
> >
> > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> > ---
> > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/kernel/cpu.c | 1 +
> > arch/riscv/kernel/cpufeature.c | 1 +
> > 4 files changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index cc1f546fdbdc..1e6d0e182be1 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -128,6 +128,12 @@ properties:
> > changes to interrupts as frozen at commit ccbddab ("Merge pull
> > request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
> >
> > + - const: smstateen
> > + description: |
> > + The standard Smstateen extension for controlling accesss to CSRs
> ^ access
>
> > + added by other Risc-V extensions in H/S/VS/U/VU modes and as
s/Risc-V/RISC-V/. Let's not invent new stylisations please.
> s/and//
>
> > + ratified at commit a28bfae (Ratified (#7)).
An "of riscv-state-enable" at the end might be helpful too.
Either way, neither checkpatch nor get_maintainer were run on this v2
patch, the former would have pointed out that dt-binding changes should
be made in their own patches.
The C stuff is fine, but this needs to be split in two.
Thanks,
Conor.
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next prev parent reply other threads:[~2023-07-21 9:07 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 7:54 [PATCH v2 0/6] Risc-V Kvm Smstateen Mayuresh Chitale
2023-07-21 7:54 ` [PATCH v2 1/6] RISC-V: Detect Smstateen extension Mayuresh Chitale
2023-07-21 8:49 ` Andrew Jones
2023-07-21 9:07 ` Conor Dooley [this message]
2023-07-21 10:11 ` Krzysztof Kozlowski
2023-07-21 7:54 ` [PATCH v2 2/6] RISC-V: KVM: Add kvm_vcpu_config Mayuresh Chitale
2023-07-21 8:53 ` Andrew Jones
2023-07-21 7:54 ` [PATCH v2 3/6] RISC-V: KVM: Enable Smstateen accesses Mayuresh Chitale
2023-07-21 8:54 ` Andrew Jones
2023-07-21 7:54 ` [PATCH v2 4/6] RISCV: KVM: Add senvcfg context save/restore Mayuresh Chitale
2023-07-21 8:55 ` Andrew Jones
2023-07-21 7:54 ` [PATCH v2 5/6] RISCV: KVM: Add sstateen0 " Mayuresh Chitale
2023-07-21 9:04 ` Andrew Jones
2023-07-21 7:54 ` [PATCH v2 6/6] RISCV: KVM: Add sstateen0 to ONE_REG Mayuresh Chitale
2023-07-21 9:13 ` Andrew Jones
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