From: Conor Dooley <conor.dooley@microchip.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 1/2] riscv: allow kmalloc() caches aligned to the smallest value
Date: Mon, 24 Jul 2023 08:49:27 +0100 [thread overview]
Message-ID: <20230724-next-shifter-3ec32114b34e@wendy> (raw)
In-Reply-To: <20230718152214.2907-2-jszhang@kernel.org>
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On Tue, Jul 18, 2023 at 11:22:13PM +0800, Jisheng Zhang wrote:
> Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E
> 64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=y. To support unified kernel
> Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus
> it brings some bad effects to coherent platforms:
>
> Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and
> kmalloc-8 slab caches don't exist any more, they are replaced with
> either kmalloc-128 or kmalloc-64.
>
> Secondly, larger than necessary kmalloc aligned allocations results
> in unnecessary cache/TLB pressure.
>
> This issue also exists on arm64 platforms. From last year, Catalin
> tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from
> ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to
> dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage
> in various drivers with ARCH_DMA_MINALIGN etc.[1]
>
> One fact we can make use of for riscv: if the CPU doesn't support
> ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on
> Catalin's work and above fact, we can easily solve the kmalloc align
> issue for riscv: we can override dma_get_cache_alignment(), then let
> it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know
> the underlying HW neither supports ZICBOM nor supports T-HEAD CMO.
>
> So what about if the CPU supports ZICBOM or T-HEAD CMO, but all the
> devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the
> kmalloc minimum alignment, nothing changed in this case. This case
> can be improved in the future.
>
> After this patch, a simple test of booting to a small buildroot rootfs
> on qemu shows:
>
> kmalloc-96 5041 5041 96 ...
> kmalloc-64 9606 9606 64 ...
> kmalloc-32 5128 5128 32 ...
> kmalloc-16 7682 7682 16 ...
> kmalloc-8 10246 10246 8 ...
>
> So we save about 1268KB memory. The saving will be much larger in normal
> OS env on real HW platforms.
>
> Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/ [1]
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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next prev parent reply other threads:[~2023-07-24 7:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-18 15:22 [PATCH v3 0/2] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
2023-07-18 15:22 ` [PATCH v3 1/2] riscv: allow kmalloc() caches aligned to the smallest value Jisheng Zhang
2023-07-24 7:49 ` Conor Dooley [this message]
2023-07-18 15:22 ` [PATCH v3 2/2] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Jisheng Zhang
2023-08-30 13:20 ` [PATCH v3 0/2] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 patchwork-bot+linux-riscv
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