From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
Conor Dooley <conor@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v4 6/7] RISCV: KVM: Add sstateen0 context save/restore
Date: Wed, 26 Jul 2023 14:13:51 +0530 [thread overview]
Message-ID: <20230726084352.2136377-7-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20230726084352.2136377-1-mchitale@ventanamicro.com>
Define sstateen0 and add sstateen0 save/restore for guest VCPUs.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/kvm_host.h | 8 ++++++++
arch/riscv/kvm/vcpu.c | 12 ++++++++++++
3 files changed, 21 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index b52270278733..5168f37d8e75 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -286,6 +286,7 @@
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
#define CSR_SENVCFG 0x10a
+#define CSR_SSTATEEN0 0x10c
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 53d1c7e1eea4..6d614022bf3e 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -170,6 +170,10 @@ struct kvm_vcpu_config {
u64 hstateen0;
};
+struct kvm_vcpu_smstateen_csr {
+ unsigned long sstateen0;
+};
+
struct kvm_vcpu_arch {
/* VCPU ran at least once */
bool ran_atleast_once;
@@ -190,6 +194,7 @@ struct kvm_vcpu_arch {
unsigned long host_stvec;
unsigned long host_scounteren;
unsigned long host_senvcfg;
+ unsigned long host_sstateen0;
/* CPU context of Host */
struct kvm_cpu_context host_context;
@@ -200,6 +205,9 @@ struct kvm_vcpu_arch {
/* CPU CSR context of Guest VCPU */
struct kvm_vcpu_csr guest_csr;
+ /* CPU Smstateen CSR context of Guest VCPU */
+ struct kvm_vcpu_smstateen_csr smstateen_csr;
+
/* CPU context upon Guest VCPU reset */
struct kvm_cpu_context guest_reset_context;
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 0f4f0d6032cc..30dd9e3261dd 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -603,16 +603,28 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *vcpu)
{
+ struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg);
+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
+ (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
+ vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0,
+ smcsr->sstateen0);
}
static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu)
{
+ struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg);
+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
+ (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
+ smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0,
+ vcpu->arch.host_sstateen0);
}
/*
--
2.34.1
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next prev parent reply other threads:[~2023-07-26 8:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-26 8:43 [PATCH v4 0/7] Risc-V Kvm Smstateen Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 1/7] RISC-V: Detect Smstateen extension Mayuresh Chitale
2023-08-03 12:01 ` Conor Dooley
2023-07-26 8:43 ` [PATCH v4 2/7] dt-bindings: riscv: Add smstateen entry Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 3/7] RISC-V: KVM: Add kvm_vcpu_config Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 4/7] RISC-V: KVM: Enable Smstateen accesses Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 5/7] RISCV: KVM: Add senvcfg context save/restore Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale [this message]
2023-07-26 8:43 ` [PATCH v4 7/7] RISCV: KVM: Add sstateen0 to ONE_REG Mayuresh Chitale
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