From: <daire.mcnamara@microchip.com>
To: <conor.dooley@microchip.com>, <lpieralisi@kernel.org>,
<kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>,
<linux-riscv@lists.infradead.org>, <linux-pci@vger.kernel.org>
Cc: Daire McNamara <daire.mcnamara@microchip.com>
Subject: [PATCH v3 1/7] PCI: microchip: Correct the DED and SEC interrupt bit offsets
Date: Fri, 28 Jul 2023 14:13:55 +0100 [thread overview]
Message-ID: <20230728131401.1615724-2-daire.mcnamara@microchip.com> (raw)
In-Reply-To: <20230728131401.1615724-1-daire.mcnamara@microchip.com>
From: Daire McNamara <daire.mcnamara@microchip.com>
The SEC and DED interrupt bits were the wrong way round so the SEC
interrupt handler attempted to mask, unmask, and clear the DED interrupt
and vice versa. Correct the bit offsets so each interrupt handler
operates properly.
Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver")
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/pci/controller/pcie-microchip-host.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 5e710e485464..dd5245904c87 100644
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -167,12 +167,12 @@
#define EVENT_PCIE_DLUP_EXIT 2
#define EVENT_SEC_TX_RAM_SEC_ERR 3
#define EVENT_SEC_RX_RAM_SEC_ERR 4
-#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5
-#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6
+#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5
+#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6
#define EVENT_DED_TX_RAM_DED_ERR 7
#define EVENT_DED_RX_RAM_DED_ERR 8
-#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9
-#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10
+#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9
+#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10
#define EVENT_LOCAL_DMA_END_ENGINE_0 11
#define EVENT_LOCAL_DMA_END_ENGINE_1 12
#define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
--
2.25.1
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next prev parent reply other threads:[~2023-07-28 13:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-28 13:13 [PATCH v3 0/7] PCI: microchip: Fixes and clean-ups daire.mcnamara
2023-07-28 13:13 ` daire.mcnamara [this message]
2023-07-28 13:13 ` [PATCH v3 2/7] PCI: microchip: Enable building driver as a module daire.mcnamara
2023-07-28 13:13 ` [PATCH v3 3/7] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara
2023-07-28 13:13 ` [PATCH v3 4/7] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara
2023-07-28 13:13 ` [PATCH v3 5/7] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara
2023-07-28 13:14 ` [PATCH v3 6/7] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara
2023-07-28 13:14 ` [PATCH v3 7/7] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara
2024-05-30 16:42 ` Bjorn Helgaas
2023-08-08 11:02 ` [PATCH v3 0/7] PCI: microchip: Fixes and clean-ups Lorenzo Pieralisi
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