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[212.5.140.29]) by smtp.gmail.com with ESMTPSA id u7-20020a170906408700b009786ae9ed50sm8651597ejj.194.2023.08.02.01.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 01:17:21 -0700 (PDT) Date: Wed, 2 Aug 2023 11:17:20 +0300 From: Andrew Jones To: Daniel Henrique Barboza Cc: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, anup@brainfault.org, atishp@atishpatra.org Subject: Re: [PATCH v2 9/9] docs: kvm: riscv: document EBUSY in KVM_SET_ONE_REG Message-ID: <20230802-4751804e563fb13903ef6277@orel> References: <20230801222629.210929-1-dbarboza@ventanamicro.com> <20230801222629.210929-10-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230801222629.210929-10-dbarboza@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230802_011725_728231_99784DBE X-CRM114-Status: GOOD ( 15.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Aug 01, 2023 at 07:26:29PM -0300, Daniel Henrique Barboza wrote: > The EBUSY errno is being used for KVM_SET_ONE_REG as a way to tell > userspace that a given reg can't be written after the vcpu started. > > Signed-off-by: Daniel Henrique Barboza > --- > Documentation/virt/kvm/api.rst | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst > index c0ddd3035462..229e7cc091c8 100644 > --- a/Documentation/virt/kvm/api.rst > +++ b/Documentation/virt/kvm/api.rst > @@ -2259,6 +2259,8 @@ Errors: > EINVAL invalid register ID, or no such register or used with VMs in > protected virtualization mode on s390 > EPERM (arm64) register access not allowed before vcpu finalization > + EBUSY (riscv) register access not allowed after the vcpu has run > + at least once We allow access (reading, even before, and now also writing when the value is the same), so this should be worded in a way that conveys the register may not be changed after the vcpu has run once. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv