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[212.5.140.29]) by smtp.gmail.com with ESMTPSA id v8-20020a17090690c800b00997e99a662bsm8741929ejw.20.2023.08.02.02.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 02:32:15 -0700 (PDT) Date: Wed, 2 Aug 2023 12:32:12 +0300 From: Andrew Jones To: Alexandre Ghiti Cc: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , =?utf-8?B?UsOpbWk=?= Denis-Courmont , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Atish Patra Subject: Re: [PATCH v6 09/10] tools: lib: perf: Implement riscv mmap support Message-ID: <20230802-7c19a712ae071f68030ab5f2@orel> References: <20230802080328.1213905-1-alexghiti@rivosinc.com> <20230802080328.1213905-10-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230802080328.1213905-10-alexghiti@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230802_023216_825040_264E5B8E X-CRM114-Status: GOOD ( 16.83 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Aug 02, 2023 at 10:03:27AM +0200, Alexandre Ghiti wrote: > riscv now supports mmaping hardware counters so add what's needed to > take advantage of that in libperf. > > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > Reviewed-by: Atish Patra > --- > tools/lib/perf/mmap.c | 66 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/tools/lib/perf/mmap.c b/tools/lib/perf/mmap.c > index 0d1634cedf44..2184814b37dd 100644 > --- a/tools/lib/perf/mmap.c > +++ b/tools/lib/perf/mmap.c > @@ -392,6 +392,72 @@ static u64 read_perf_counter(unsigned int counter) > > static u64 read_timestamp(void) { return read_sysreg(cntvct_el0); } > > +/* __riscv_xlen contains the witdh of the native base integer, here 64-bit */ > +#elif defined(__riscv) && __riscv_xlen == 64 > + > +/* TODO: implement rv32 support */ > + > +#define CSR_CYCLE 0xc00 > +#define CSR_TIME 0xc01 > + > +#define csr_read(csr) \ > +({ \ > + register unsigned long __v; \ > + __asm__ __volatile__ ("csrr %0, %1" \ > + : "=r" (__v) \ > + : "i" (csr) : ); \ > + __v; \ nit: no need for the indentation or line wrap, ({ register unsigned long __v; __asm__ __volatile__ ("csrr %0, %1" : "=r" (__v) : "i" (csr)); __v; }) Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv