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[212.5.140.29]) by smtp.gmail.com with ESMTPSA id gy26-20020a170906f25a00b00992b7ff3993sm9988601ejb.126.2023.08.03.00.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 00:04:51 -0700 (PDT) Date: Thu, 3 Aug 2023 10:04:50 +0300 From: Andrew Jones To: Guo Ren Cc: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, virtualization@lists.linux-foundation.org, 'Paul Walmsley ' , 'Albert Ou ' , 'Palmer Dabbelt ' , 'Paolo Bonzini ' , 'Juergen Gross ' , "'Srivatsa S . Bhat '" , 'Anup Patel ' , 'Atish Patra ' Subject: Re: [RFC PATCH 03/14] RISC-V: paravirt: Implement steal-time support Message-ID: <20230803-61c4bc90486e17560b338272@orel> References: <20230417103402.798596-1-ajones@ventanamicro.com> <20230417103402.798596-4-ajones@ventanamicro.com> <245mmbzeqcap7i6cjmoaaitpmecefjo2ul63qjmodjv77uz54e@tizorx3p64fz> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230803_000455_503243_62321475 X-CRM114-Status: GOOD ( 33.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Aug 02, 2023 at 07:26:53PM -0400, Guo Ren wrote: > On Wed, Apr 19, 2023 at 10:42:16AM +0200, Andrew Jones wrote: > > On Mon, Apr 17, 2023 at 12:33:51PM +0200, Andrew Jones wrote: > > > When the SBI STA extension exists we can use it to implement > > > paravirt steal-time support. Fill in the empty pv-time functions > > > with an SBI STA implementation. > > > > > > Signed-off-by: Andrew Jones > > > --- > > > arch/riscv/kernel/paravirt.c | 56 ++++++++++++++++++++++++++++++++++-- > > > 1 file changed, 53 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/riscv/kernel/paravirt.c b/arch/riscv/kernel/paravirt.c > > > index 141dbcc36fa2..5f8d96b919e4 100644 > > > --- a/arch/riscv/kernel/paravirt.c > > > +++ b/arch/riscv/kernel/paravirt.c > > > @@ -6,12 +6,21 @@ > > > #define pr_fmt(fmt) "riscv-pv: " fmt > > > > > > #include > > > +#include > > > +#include > > > #include > > > #include > > > +#include > > > +#include > > > +#include > > > #include > > > #include > > > #include > > > > > > +#include > > > +#include > > > +#include > > > + > > > struct static_key paravirt_steal_enabled; > > > struct static_key paravirt_steal_rq_enabled; > > > > > > @@ -31,24 +40,65 @@ static int __init parse_no_stealacc(char *arg) > > > > > > early_param("no-steal-acc", parse_no_stealacc); > > > > > > +DEFINE_PER_CPU(struct sbi_sta_struct, steal_time) __aligned(64); > > > + > > > static bool __init has_pv_steal_clock(void) > > > { > > > + if (sbi_probe_extension(SBI_EXT_STA) > 0) { > > > + pr_info("SBI STA extension detected\n"); > > > + return true; > > > + } > > > + > > > return false; > > > } > > > > > > -static int pv_time_cpu_online(unsigned int cpu) > > > +static int sbi_sta_set_steal_time_shmem(unsigned long lo, unsigned long hi, > > > + unsigned long flags) > > > { > > > + struct sbiret ret; > > > + > > > + ret = sbi_ecall(SBI_EXT_STA, SBI_EXT_STA_SET_STEAL_TIME_SHMEM, > > > + lo, hi, flags, 0, 0, 0); > > > + if (ret.error) { > > > + if (lo == -1 && hi == -1) > > > + pr_warn("Failed to disable steal-time shmem"); > > > + else > > > + pr_warn("Failed to set steal-time shmem"); > > > + return -ENOMEM; > > > + } > > > + > > > return 0; > > > } > > > > > > +static int pv_time_cpu_online(unsigned int cpu) > > > +{ > > > + struct sbi_sta_struct *st = this_cpu_ptr(&steal_time); > > > + phys_addr_t pa = __pa(st); > > > + unsigned long lo = (unsigned long)pa; > > > + unsigned long hi = IS_ENABLED(CONFIG_32BIT) ? upper_32_bits((u64)pa) : 0; > > > + > > > + return sbi_sta_set_steal_time_shmem(lo, hi, 0); > > > +} > > > + > > > static int pv_time_cpu_down_prepare(unsigned int cpu) > > > { > > > - return 0; > > > + return sbi_sta_set_steal_time_shmem(-1, -1, 0); > > > } > > > > > > static u64 pv_time_steal_clock(int cpu) > > > { > > > - return 0; > > > + struct sbi_sta_struct *st = per_cpu_ptr(&steal_time, cpu); > > > + u32 sequence; > > > + u64 steal; > > > + > > > + do { > > > + sequence = st->sequence; > > > + virt_rmb(); > > > + steal = st->steal; > > > + virt_rmb(); > > > + } while ((sequence & 1) || (sequence != st->sequence)); > > > + > > > + return steal; > > > } > > > > So anybody poking around the implementations for other architectures will > > see that I shamelessly ripped this off from x86's implementation. However, > > looking at it again, I think all the references to the steal-time info > > should be wrapped in READ_ONCE(). I'll write a patch for x86/kvm to > > add READ_ONCE's and also update this patch for rfc-v2. > Hello, what's the status of rfc-v2? The riscv paravirt_qspinlock is > based on your series to reuse the paravirt.c and CONFIG_PARAVIRT. I prepared it, but then didn't bother posting, since the series has to stay an RFC and not be merged until the spec is frozen and the changes were pretty minor (mostly just name changes). The pv_time_steal_clock() changes described above look like this static u64 pv_time_steal_clock(int cpu) { struct sbi_sta_struct *st = per_cpu_ptr(&steal_time, cpu); u32 sequence; u64 steal; /* * Check the sequence field before and after reading the steal * field. Repeat the read if it is different or odd. */ do { sequence = READ_ONCE(st->sequence); virt_rmb(); steal = READ_ONCE(st->steal); virt_rmb(); } while ((le32_to_cpu(sequence) & 1) || sequence != READ_ONCE(st->sequence)); return le64_to_cpu(steal); } > > https://lore.kernel.org/linux-riscv/20230802164701.192791-10-guoren@kernel.org/ > https://lore.kernel.org/linux-riscv/20230802164701.192791-17-guoren@kernel.org/ Thanks, I'll take a look at this. drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv