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[212.5.140.29]) by smtp.gmail.com with ESMTPSA id n10-20020aa7c44a000000b0052238bc70ccsm9745891edr.89.2023.08.03.00.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 00:20:33 -0700 (PDT) Date: Thu, 3 Aug 2023 10:20:32 +0300 From: Andrew Jones To: Guo Ren Cc: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, virtualization@lists.linux-foundation.org, 'Paul Walmsley ' , 'Albert Ou ' , 'Palmer Dabbelt ' , 'Paolo Bonzini ' , 'Juergen Gross ' , "'Srivatsa S . Bhat '" , 'Anup Patel ' , 'Atish Patra ' Subject: Re: [RFC PATCH 02/14] RISC-V: Add SBI STA extension definitions Message-ID: <20230803-73f12efe1a16517072404251@orel> References: <20230417103402.798596-1-ajones@ventanamicro.com> <20230417103402.798596-3-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230803_002041_929346_8034D709 X-CRM114-Status: GOOD ( 25.04 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Aug 02, 2023 at 07:32:48PM -0400, Guo Ren wrote: > On Mon, Apr 17, 2023 at 12:33:50PM +0200, Andrew Jones wrote: > > The SBI STA extension enables steal-time accounting. Add the > > definitions it specifies. > > > > Signed-off-by: Andrew Jones > > --- > > arch/riscv/include/asm/sbi.h | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > > index 945b7be249c1..485b9ec20399 100644 > > --- a/arch/riscv/include/asm/sbi.h > > +++ b/arch/riscv/include/asm/sbi.h > > @@ -30,6 +30,7 @@ enum sbi_ext_id { > > SBI_EXT_HSM = 0x48534D, > > SBI_EXT_SRST = 0x53525354, > > SBI_EXT_PMU = 0x504D55, > > + SBI_EXT_STA = 0x535441, > > > > /* Experimentals extensions must lie within this range */ > > SBI_EXT_EXPERIMENTAL_START = 0x08000000, > > @@ -236,6 +237,20 @@ enum sbi_pmu_ctr_type { > > /* Flags defined for counter stop function */ > > #define SBI_PMU_STOP_FLAG_RESET (1 << 0) > > > > +/* SBI STA (steal-time accounting) extension */ > > +enum sbi_ext_sta_fid { > > + SBI_EXT_STA_SET_STEAL_TIME_SHMEM = 0, > > +}; > > + > > +struct sbi_sta_struct { > > + __le32 sequence; > > + __le32 flags; > > + __le64 steal; > Could we wrap the "sequence & steal" into one 64-bit variable? Then only > rv32 needs double READs, and only one ld instruction for rv64 ISA. That's possible, but we'd have to reduce the size of steal by whatever size we decide is sufficient for sequence. In order to do that we'll need to discuss the size reduction proposals and their justifications at the spec level. If you'd like to make that proposal, then please create an issue at [1]. But, I don't think it should be necessary. There's non-normative text in the spec that says "This sequence field enables the value of the steal field to be read by supervisor-mode software executing in a 32-bit environment.", which implies to me that we could optimize the read in a 64-bit environment by neglecting to read sequence at all. [1] https://github.com/riscv-non-isa/riscv-sbi-doc Thanks, drew > > > + u8 preempted; > > + u8 pad[47]; > > +} __packed; > > + > > +/* SBI spec version fields */ > > #define SBI_SPEC_VERSION_DEFAULT 0x1 > > #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 > > #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f > > -- > > 2.39.2 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv