[PATCH] drivers/perf: Risc-V: Update platform specific firmware event handling

* [PATCH] drivers/perf: Risc-V: Update platform specific firmware event handling
@ 2023-08-14  4:31 Mayuresh Chitale
  2023-08-15 13:14 ` Conor Dooley
  2023-08-15 13:19 ` Conor Dooley
  0 siblings, 2 replies; 4+ messages in thread
From: Mayuresh Chitale @ 2023-08-14  4:31 UTC (permalink / raw)
  To: Atish Patra, Anup Patel
  Cc: Mayuresh Chitale, Andrew Jones, Paul Walmsley, Palmer Dabbelt,
	Albert Ou, Will Deacon, Mark Rutland, Heiko Stuebner,
	Conor Dooley, linux-riscv

SBI specification [1] reserves an event code for platform specific
firmware events. Update the driver to use the new reserved event code
for platform specific firmware events. Also update the raw event parsing
to use bits 63:62 instead of only bit 63 to distinguish between the raw
event types. The platform specific firmware events must be specified in
the perf command as in the below example:
perf stat  -e rc000000000000001 <command>
where [63:62] = 0x3 indicates a platform specific firmware event

Link: https://github.com/riscv-non-isa/riscv-sbi-doc/commit/c4bfdf9 [1]
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
 arch/riscv/include/asm/sbi.h |  1 +
 drivers/perf/riscv_pmu_sbi.c | 29 +++++++++++++++++++++--------
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..001387354c2e 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -138,6 +138,7 @@ union sbi_pmu_ctr_info {
 
 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
 #define RISCV_PMU_RAW_EVENT_IDX 0x20000
+#define RISCV_PLAT_FW_EVENT	0xFFFF
 
 /** General pmu event codes specified in SBI PMU extension */
 enum sbi_pmu_hw_generic_events_t {
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 4163ff517471..f94a3f0a469b 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -414,7 +414,6 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
 {
 	u32 type = event->attr.type;
 	u64 config = event->attr.config;
-	int bSoftware;
 	u64 raw_config_val;
 	int ret;
 
@@ -429,18 +428,32 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
 		break;
 	case PERF_TYPE_RAW:
 		/*
-		 * As per SBI specification, the upper 16 bits must be unused for
-		 * a raw event. Use the MSB (63b) to distinguish between hardware
-		 * raw event and firmware events.
+		 * As per SBI specification, the upper 16 bits must be unused
+		 * for a raw event. Hence bits 63:62 are used to distinguish
+		 * between raw events:
+		 * 00 - Hardware raw event
+		 * 10 - SBI firmware events
+		 * 11 - Risc-V platform specific firmware event
 		 */
-		bSoftware = config >> 63;
 		raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
-		if (bSoftware) {
+		switch (config >> 62) {
+		case 0:
+			ret = RISCV_PMU_RAW_EVENT_IDX;
+			*econfig = raw_config_val;
+			break;
+		case 2:
 			ret = (raw_config_val & 0xFFFF) |
 				(SBI_PMU_EVENT_TYPE_FW << 16);
-		} else {
-			ret = RISCV_PMU_RAW_EVENT_IDX;
+			break;
+		case 3:
+			/*
+			 * For Risc-V platform specific firmware events
+			 * Event code - 0xFFFF
+			 * Event data - raw event encoding
+			 */
+			ret = SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT;
 			*econfig = raw_config_val;
+			break;
 		}
 		break;
 	default:
-- 
2.34.1


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