From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86938C83F11 for ; Mon, 28 Aug 2023 18:56:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qde0tvj9b6LQO+owEf+l8er/p7DVMUBrWqKQgzq4CN4=; b=2HPm8dolZURCBoWWNrmCzTYtCk KckP6LG9y6k+PMExL3Zldf/73phpiZKoEjcVSmGAr0XMpCiZeJFNbqnNtP8P1AiWlEdy2kX36Z8mo Fr13pczU3IHNUy0S7KhAPcNdNtldbMuLK6V/tmVuKI2PCYMQrVReG8Y4ggLiUZpbJGr23TCegNhjj Dppl3/8nLVB45Xh/cfmXZWA6PIaRDngCVcJjTQsgjUlgyYfSRAgJp8O18eD8pXW2mlwINbLUpdtr8 jceVtkXcG0tuIsUbJPg5u3fl9q+/qhrLgEm5DIW5+jZA73pmIWOPjk0O8DzXgVN6G6gXhiDbgARV+ q1hWJr8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qahPS-00A6iH-0y; Mon, 28 Aug 2023 18:56:22 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qahPO-00A6hZ-0m for linux-riscv@lists.infradead.org; Mon, 28 Aug 2023 18:56:20 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 84BAC628B7; Mon, 28 Aug 2023 18:56:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F8EFC433C9; Mon, 28 Aug 2023 18:56:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693248976; bh=OFhBnwoewdY+qFYoIfWuNLyfHMpvi+KJxJhwtNw6GgA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Zg6Q5crmZhvX/zWOef3Sx7nkTyzGvtGtiyajLC5yJYEhHdzRP3T9nwWNclwFtyE0n t6yEbqVVYFIsHh0uTSc5NfxFMnCq5UhsdUBS6n/qriEl8wnKvdqYiRChOaGHH8B0Y6 LcJoAV+9yoyeomjyJpI5SskUX2b7C2cJ14s323FpDnZOiTfN3TpAm+BEnL+uCJY/bA ht1G1crYB2RnOOL8qZXnGMM/nwH8jZZfrA+4HSDUJI1GKEP/OWnU22FoEQjMd7dGtu rD9I3l8Dh9kG3bNnXeOwAq2uB6F8d7F2CcoEWGs6fazPz1jaGR2k985cjwSmUdMFyc Ug9802jZne0GQ== Date: Mon, 28 Aug 2023 19:56:13 +0100 From: Conor Dooley To: Charlie Jenkins Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley , aou@eecs.berkeley.edu Subject: Re: [PATCH 1/5] riscv: Checksum header Message-ID: <20230828-stonewall-eloquence-8940f33bd2f0@spud> References: <20230827-turf-parched-b965bc697882@spud> <20230827-primer-conceal-b6f24b29e692@spud> <20230827-divisive-happy-cf93058c49bf@spud> <20230828-deserve-paging-25666290e312@spud> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230828_115618_365048_4815326F X-CRM114-Status: GOOD ( 74.08 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============9053014724122128696==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============9053014724122128696== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7xRodtzpcS727W/L" Content-Disposition: inline --7xRodtzpcS727W/L Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 28, 2023 at 11:20:39AM -0700, Charlie Jenkins wrote: > On Mon, Aug 28, 2023 at 06:08:40PM +0100, Conor Dooley wrote: > > On Mon, Aug 28, 2023 at 09:55:49AM -0700, Charlie Jenkins wrote: > > > On Sun, Aug 27, 2023 at 01:25:27PM +0100, Conor Dooley wrote: > > > > On Sun, Aug 27, 2023 at 11:28:33AM +0100, Conor Dooley wrote: > > > > > On Sat, Aug 26, 2023 at 07:00:47PM -0700, Palmer Dabbelt wrote: > > > > > > On Sat, 26 Aug 2023 18:42:41 PDT (-0700), Conor Dooley wrote: > > > > > > > On Sat, Aug 26, 2023 at 06:26:06PM -0700, Charlie Jenkins wro= te: > > > > > > > > Provide checksum algorithms that have been designed to leve= rage riscv > > > > > > > > instructions such as rotate. In 64-bit, can take advantage = of the larger > > > > > > > > register to avoid some overflow checking. > > > > > > > >=20 > > > > > > > > Add configuration for Zba extension and add march for Zba a= nd Zbb. > > > > > > > >=20 > > > > > > > > Signed-off-by: Charlie Jenkins > > > > > > > > --- > > > > > > > > arch/riscv/Kconfig | 23 +++++++++++ > > > > > > > > arch/riscv/Makefile | 2 + > > > > > > > > arch/riscv/include/asm/checksum.h | 86 +++++++++++++++++++= ++++++++++++++++++++ > > > > > > > > 3 files changed, 111 insertions(+) > > > > > > > >=20 > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > > > > > > index 4c07b9189c86..8d7e475ca28d 100644 > > > > > > > > --- a/arch/riscv/Kconfig > > > > > > > > +++ b/arch/riscv/Kconfig > > > > > > > > @@ -507,6 +507,29 @@ config RISCV_ISA_V_DEFAULT_ENABLE > > > > > > > > If you don't know what to do here, say Y. > > > > > > > > +config TOOLCHAIN_HAS_ZBA > > > > > > > > + bool > > > > > > > > + default y > > > > > > > > + depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv= 64ima_zba) > > > > > > > > + depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Dr= v32ima_zba) > > > > > > > > + depends on LLD_VERSION >=3D 150000 || LD_VERSION >=3D 239= 00 > > > > > > > > + depends on AS_HAS_OPTION_ARCH > > > > > > > > + > > > > > > > > +config RISCV_ISA_ZBA > > > > > > > > + bool "Zba extension support for bit manipulation instruct= ions" > > > > > > > > + depends on TOOLCHAIN_HAS_ZBA > > > > > > > > + depends on MMU > > > > > > > > + depends on RISCV_ALTERNATIVE > > > > > > > > + default y > > > > > > > > + help > > > > > > > > + Adds support to dynamically detect the presence of the= ZBA > > > > > > > > + extension (basic bit manipulation) and enable its usag= e. > > > > > > > > + > > > > > > > > + The Zba extension provides instructions to accelerate = a number > > > > > > > > + of bit-specific address creation operations. > > > > > > > > + > > > > > > > > + If you don't know what to do here, say Y. > > > > > > > > + > > > > > > > > config TOOLCHAIN_HAS_ZBB > > > > > > > > bool > > > > > > > > default y > > > > > > > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > > > > > > > > index 6ec6d52a4180..51fa3f67fc9a 100644 > > > > > > > > --- a/arch/riscv/Makefile > > > > > > > > +++ b/arch/riscv/Makefile > > > > > > > > @@ -61,6 +61,8 @@ riscv-march-$(CONFIG_ARCH_RV64I) :=3D rv6= 4ima > > > > > > > > riscv-march-$(CONFIG_FPU) :=3D $(riscv-march-y)fd > > > > > > > > riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c > > > > > > > > riscv-march-$(CONFIG_RISCV_ISA_V) :=3D $(riscv-march-y)v > > > > > > > > +riscv-march-$(CONFIG_RISCV_ISA_ZBA) :=3D $(riscv-march-y)_= zba > > > > > > > > +riscv-march-$(CONFIG_RISCV_ISA_ZBB) :=3D $(riscv-march-y)_= zbb > > > > > > >=20 > > > > > > > AFAICT, this is going to break immediately on any system that= enables > > > > > > > RISCV_ISA_ZBA (which will happen by default) but does not sup= port the > > > > > > > extension. You made the option depend on RISCV_ALTERNATIVE, b= ut I do > > > > > > > not see any use of alternatives in the code to actually perfo= rm the > > > > > > > dynamic detection of Zba. > > > > > >=20 > > > > > > I guess we kind of have an ambiguity here: for stuff like C we = just > > > > > > unconditionally use the instructions, but for the rest we probe= first. We > > > > > > should probably have three states for each extension: disabled,= dynamically > > > > > > detected, and assumed. > > > > >=20 > > > > > You mean, just add some comments to the makefile surrounding each > > > > > section or to some rst documentation? > > > >=20 > > > > Also, the code here doesn't build w/ > > > > warning: invalid argument to '-march': '_zba_zbb_zicsr_zifencei_zi= hintpause' > > > > so there's something else wrong with TOOLCHAIN_HAS_ZBA :) > > > It is odd that this is missing 'rv64ima' or 'rv32ima' at the beginnin= g of > > > this string. What configuration are you using that could cause that to > > > be left off? > >=20 > > I don't know, but that configuration is pretty pervasive. The patchwork > > CI blew up too & that is using kernel.org toolchains built by Arnd: > > https://mirrors.edge.kernel.org/pub/tools/crosstool/ > >=20 > > > Compiling with defconfig automatically enables Zba and appears to not > > > cause this issue. I realized that I put the header definitions for > > > do_csum and csum_ipv6_magic in this patch instead of the next one so = the > > > code will fail to compile from this but not due to march settings. > > > >=20 > > > > >=20 > > > > > > > Note that for fd & v, we add it to riscv-march-y, but then im= mediately > > > > > > > remove it again before passing to the compiler, only allow th= em in > > > > > > > AFLAGS: > > > > > > > # Remove F,D,V from isa string for all. Keep extensions betw= een "fd" and "v" by > > > > > > > # matching non-v and non-multi-letter extensions out with th= e filter ([^v_]*) > > > > > > > KBUILD_CFLAGS +=3D -march=3D$(shell echo $(riscv-march-y) | = sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/') > > > > > > >=20 > > > > > > > What am I missing? > > > > > >=20 > > > > > > FD and V both have state that can be saved lazily, so we can't = let arbitrary > > > > > > code use them. The extensions formally known as B don't add st= ate, so they > > > > > > are safe to flip on in arbitrary places (aside from the issues = you pointed > > > > > > out above). > > > > >=20 > > > > > I probably went about this badly since you missed the point. I was > > > > > trying to point out that for anything other than the compressed > > > > > extensions in the block above that we only pass them in march to = the > > > > > assembler, and not to the compiler, in contrast to this patch whi= ch just > > > > > always passes them. I should have pointed to how we handled the > > > > > in-kernel Zbb stuff & asked how this was any different, would pro= bably > > > > > have been clearer. > > > > >=20 > > > I supposed it might be better if I submit these changes in a different > > > patch so we can have more discussion there. Zbb was previously only u= sed > > > by assembly files (arch/riscv/lib/strcmp.S, arch/riscv/lib/strlen.S, > > > arch/riscv/lib/strncmp.S). I wanted to add them to the compiler so th= at > > > that C programs could leverage these extensions. However, I neglected= to > > > consider machines that compile the kernel with these extensions but h= ave > > > cores without these extensions. > >=20 > > Less so cores, since we don't support heterogeneous stuff, and moreso > > platforms that do not support the extensions. It's expected that the > > same kernel could in theory be used across a wide variety of systems. > >=20 > > > The purpose of using these extensions is > > > to save a couple of clock cycles, so if it is necessary to first > > > check if the extension is enabled it may not be worth it for these > > > functions. > >=20 > > That's still possible, it's what the alternatives mechanism exists for. > > During boot the codepaths are patched to use what works for a given > > machine, check out the code that makes use of Zbb or > > riscv_has_extension_[un]likely(). You'd need to do something like the > > existing users of Zbb instructions does, with an alternative used to > > avoid the custom asm implementations when the hardware does not support > > them. (That's what the CONFIG_ALTERNATIVE & CONFIG_AS_HAS_OPTION_ARCH > > options you made the TOOLCHAIN_HAS_ZBA depend on are for). >=20 > I can see how to get this to work if I port this code into assembly and > write two different versions (one with Zbb and one without), but > I don't see how this would work in C. Unless I am mistaken, there would > need to be some sort of wrapper around the C code that told the compiler > to compile it multiple times for different extension combinations and > then use the riscv_has_extension_[un]likely() functions to determine > which version to use at runtime. Is this feasible? IIRC, if you put all the code using Zbb etc into a compilation unit of its own then you can set march for that unit alone, but it may well just be easier to write a custom asm one for the Zbb case & use the c implementation from this patch for the non-Zbb case. --7xRodtzpcS727W/L Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZOztzQAKCRB4tDGHoIJi 0hRcAP0blwoDSEoeC2O8hY3MGRrsAzmDs/uG7nzr+5e7pdnwxAD/RgC2+MSV18Rs wUV26acA15AfVsOOMS2Y9eWgMkJ8Vw8= =7lrP -----END PGP SIGNATURE----- --7xRodtzpcS727W/L-- --===============9053014724122128696== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============9053014724122128696==--