Re: [PATCH] riscv: provide riscv-specific is_trap_insn()

From: Conor Dooley <conor.dooley@microchip.com>
To: Guo Ren <guoren@kernel.org>
Cc: Nam Cao <namcaov@gmail.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<bjorn@kernel.org>
Subject: Re: [PATCH] riscv: provide riscv-specific is_trap_insn()
Date: Tue, 29 Aug 2023 07:26:54 +0100	[thread overview]
Message-ID: <20230829-unbridle-condense-2fc45a442bb6@wendy> (raw)
In-Reply-To: <CAJF2gTQysBBSbtFcx1uY_ztTnzN5jRWpG2OD4O3aJ0u9Ekwsag@mail.gmail.com>

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On Tue, Aug 29, 2023 at 01:56:34PM +0800, Guo Ren wrote:
> On Mon, Aug 28, 2023 at 4:56 AM Nam Cao <namcaov@gmail.com> wrote:
> >
> > uprobes expects is_trap_insn() to return true for any trap instructions,
> > not just the one used for installing uprobe. The current default
> > implementation only returns true for 16-bit c.ebreak if C extension is
> > enabled. This can confuse uprobes if a 32-bit ebreak generates a trap
> > exception from userspace: uprobes asks is_trap_insn() who says there is no
> > trap, so uprobes assume a probe was there before but has been removed, and
> > return to the trap instruction. This cause an infinite loop of entering
> > and exiting trap handler.
> >
> > Instead of using the default implementation, implement this function
> > speficially for riscv which checks for both ebreak and c.ebreak.
> >
> > Fixes: 74784081aac8 ("riscv: Add uprobes supported")
> > Signed-off-by: Nam Cao <namcaov@gmail.com>
> > ---
> >  arch/riscv/kernel/probes/uprobes.c | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/probes/uprobes.c b/arch/riscv/kernel/probes/uprobes.c
> > index 194f166b2cc4..91f4ce101cd1 100644
> > --- a/arch/riscv/kernel/probes/uprobes.c
> > +++ b/arch/riscv/kernel/probes/uprobes.c
> > @@ -3,6 +3,7 @@
> >  #include <linux/highmem.h>
> >  #include <linux/ptrace.h>
> >  #include <linux/uprobes.h>
> > +#include <asm/insn.h>
> >
> >  #include "decode-insn.h"
> >
> > @@ -17,6 +18,15 @@ bool is_swbp_insn(uprobe_opcode_t *insn)
> >  #endif
> >  }
>  >
> > +bool is_trap_insn(uprobe_opcode_t *insn)
> > +{
> > +#ifdef CONFIG_RISCV_ISA_C

> Can we remove the CONFIG_RISCV_ISA_C? As you said, "uprobes expects
> is_trap_insn() to return true for any trap instructions". So userspace
> wouldn't be limited by CONFIG_RISCV_ISA_C.

Isn't the RISCV_ISA_C required because there's a different encoding for
EBREAK vs C_EBREAK? That said, this should be using IS_ENABLED() not
#ifdef, since the definition for riscv_insn_is_c_ebreak() is provided
unconditionally afaict.

> 
> > +       if (riscv_insn_is_c_ebreak(*insn))
> > +               return true;
> > +#endif
> > +       return riscv_insn_is_ebreak(*insn);
> > +}
> > +
> >  unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
> >  {
> >         return instruction_pointer(regs);
> > --
> > 2.34.1
> >

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