From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, evan@rivosinc.com,
conor.dooley@microchip.com, apatel@ventanamicro.com
Subject: Re: [PATCH v2 0/6] RISC-V: Enable cbo.zero in usermode
Date: Wed, 30 Aug 2023 18:52:46 +0200 [thread overview]
Message-ID: <20230830-367b41474b33b230aa3f0c3a@orel> (raw)
In-Reply-To: <20230830164954.91987-8-ajones@ventanamicro.com>
On Wed, Aug 30, 2023 at 06:49:55PM +0200, Andrew Jones wrote:
> In order for usermode to issue cbo.zero, it needs privilege granted to
> issue the extension instruction (patch 2) and to know that the extension
> is available and its block size (patch 3). Patch 1 could be separate from
> this series (it just fixes up some error messages), patches 4-5 convert
> the hwprobe selftest to a statically-linked, TAP test and patch 6 adds a
> new hwprobe test for the new information as well as testing CBO
> instructions can or cannot be issued as appropriate.
>
> Thanks,
> drew
>
> v2:
> - fixed build of the vector selftest
for-next also needs commit 25696067202f ("selftests: riscv: Fix
compilation error with vstate_exec_nolibc.c") in order for the vector
selftest to build.
Thanks,
drew
> - changed this-cpu wrappers to just cpu wrappers and then pass
> smp_processor_id() at the callsite
> - added comment to EXT_KEY macro
> - picked up a couple r-b's
>
> Andrew Jones (6):
> RISC-V: Make zicbom/zicboz errors consistent
> RISC-V: Enable cbo.zero in usermode
> RISC-V: hwprobe: Expose Zicboz extension and its block size
> RISC-V: selftests: Statically link hwprobe test
> RISC-V: selftests: Convert hwprobe test to kselftest API
> RISC-V: selftests: Add CBO tests
>
> Documentation/riscv/hwprobe.rst | 6 +
> arch/riscv/include/asm/cpufeature.h | 2 +
> arch/riscv/include/asm/csr.h | 1 +
> arch/riscv/include/asm/hwcap.h | 16 ++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 2 +
> arch/riscv/kernel/cpufeature.c | 10 +-
> arch/riscv/kernel/setup.c | 4 +
> arch/riscv/kernel/smpboot.c | 4 +
> arch/riscv/kernel/sys_riscv.c | 46 +++--
> .../testing/selftests/riscv/hwprobe/Makefile | 9 +-
> tools/testing/selftests/riscv/hwprobe/cbo.c | 162 ++++++++++++++++++
> .../testing/selftests/riscv/hwprobe/hwprobe.c | 64 +++----
> .../testing/selftests/riscv/hwprobe/hwprobe.h | 15 ++
> 14 files changed, 280 insertions(+), 63 deletions(-)
> create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c
> create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h
>
> --
> 2.41.0
>
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next prev parent reply other threads:[~2023-08-30 16:52 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-30 16:49 [PATCH v2 0/6] RISC-V: Enable cbo.zero in usermode Andrew Jones
2023-08-30 16:49 ` [PATCH v2 1/6] RISC-V: Make zicbom/zicboz errors consistent Andrew Jones
2023-08-30 16:49 ` [PATCH v2 2/6] RISC-V: Enable cbo.zero in usermode Andrew Jones
2023-08-31 16:24 ` Conor Dooley
2023-08-31 16:39 ` Andrew Jones
2023-08-31 16:46 ` Conor Dooley
2023-08-30 16:49 ` [PATCH v2 3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size Andrew Jones
2023-08-31 16:19 ` Conor Dooley
2023-08-30 16:49 ` [PATCH v2 4/6] RISC-V: selftests: Statically link hwprobe test Andrew Jones
2023-08-30 16:50 ` [PATCH v2 5/6] RISC-V: selftests: Convert hwprobe test to kselftest API Andrew Jones
2023-08-30 16:50 ` [PATCH v2 6/6] RISC-V: selftests: Add CBO tests Andrew Jones
2023-09-01 9:37 ` Wang, Xiao W
2023-09-01 15:12 ` Andrew Jones
2023-08-30 16:52 ` Andrew Jones [this message]
2023-08-30 20:28 ` [PATCH v2 0/6] RISC-V: Enable cbo.zero in usermode Palmer Dabbelt
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