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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id b3-20020adfde03000000b0031accc7228asm17091833wrm.34.2023.08.30.09.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 09:52:47 -0700 (PDT) Date: Wed, 30 Aug 2023 18:52:46 +0200 From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, evan@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com Subject: Re: [PATCH v2 0/6] RISC-V: Enable cbo.zero in usermode Message-ID: <20230830-367b41474b33b230aa3f0c3a@orel> References: <20230830164954.91987-8-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230830164954.91987-8-ajones@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230830_095250_518636_2BDA5580 X-CRM114-Status: GOOD ( 19.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Aug 30, 2023 at 06:49:55PM +0200, Andrew Jones wrote: > In order for usermode to issue cbo.zero, it needs privilege granted to > issue the extension instruction (patch 2) and to know that the extension > is available and its block size (patch 3). Patch 1 could be separate from > this series (it just fixes up some error messages), patches 4-5 convert > the hwprobe selftest to a statically-linked, TAP test and patch 6 adds a > new hwprobe test for the new information as well as testing CBO > instructions can or cannot be issued as appropriate. > > Thanks, > drew > > v2: > - fixed build of the vector selftest for-next also needs commit 25696067202f ("selftests: riscv: Fix compilation error with vstate_exec_nolibc.c") in order for the vector selftest to build. Thanks, drew > - changed this-cpu wrappers to just cpu wrappers and then pass > smp_processor_id() at the callsite > - added comment to EXT_KEY macro > - picked up a couple r-b's > > Andrew Jones (6): > RISC-V: Make zicbom/zicboz errors consistent > RISC-V: Enable cbo.zero in usermode > RISC-V: hwprobe: Expose Zicboz extension and its block size > RISC-V: selftests: Statically link hwprobe test > RISC-V: selftests: Convert hwprobe test to kselftest API > RISC-V: selftests: Add CBO tests > > Documentation/riscv/hwprobe.rst | 6 + > arch/riscv/include/asm/cpufeature.h | 2 + > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/include/asm/hwcap.h | 16 ++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 2 + > arch/riscv/kernel/cpufeature.c | 10 +- > arch/riscv/kernel/setup.c | 4 + > arch/riscv/kernel/smpboot.c | 4 + > arch/riscv/kernel/sys_riscv.c | 46 +++-- > .../testing/selftests/riscv/hwprobe/Makefile | 9 +- > tools/testing/selftests/riscv/hwprobe/cbo.c | 162 ++++++++++++++++++ > .../testing/selftests/riscv/hwprobe/hwprobe.c | 64 +++---- > .../testing/selftests/riscv/hwprobe/hwprobe.h | 15 ++ > 14 files changed, 280 insertions(+), 63 deletions(-) > create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c > create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h > > -- > 2.41.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv