From: Andrew Jones <ajones@ventanamicro.com>
To: "Wang, Xiao W" <xiao.w.wang@intel.com>
Cc: "linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"evan@rivosinc.com" <evan@rivosinc.com>,
"conor.dooley@microchip.com" <conor.dooley@microchip.com>,
"apatel@ventanamicro.com" <apatel@ventanamicro.com>
Subject: Re: [PATCH v2 6/6] RISC-V: selftests: Add CBO tests
Date: Fri, 1 Sep 2023 17:12:08 +0200 [thread overview]
Message-ID: <20230901-b4e5f6219de94391e5fa11d6@orel> (raw)
In-Reply-To: <DM8PR11MB57513A1848E33ABF9131423AB8E4A@DM8PR11MB5751.namprd11.prod.outlook.com>
On Fri, Sep 01, 2023 at 09:37:27AM +0000, Wang, Xiao W wrote:
> Hi,
>
> > -----Original Message-----
> > From: linux-riscv <linux-riscv-bounces@lists.infradead.org> On Behalf Of
> > Andrew Jones
> > Sent: Thursday, August 31, 2023 12:50 AM
> > To: linux-riscv@lists.infradead.org
> > Cc: paul.walmsley@sifive.com; palmer@dabbelt.com;
> > aou@eecs.berkeley.edu; evan@rivosinc.com; conor.dooley@microchip.com;
> > apatel@ventanamicro.com
> > Subject: [PATCH v2 6/6] RISC-V: selftests: Add CBO tests
> >
> > Add hwprobe test for Zicboz and its block size. Also, when Zicboz is
> > present, test that cbo.zero may be issued and works. Additionally
> > test that the Zicbom instructions cause SIGILL and also that cbo.zero
> > causes SIGILL when Zicboz is not present. Pinning the test to a subset
> > of cpus with taskset will also restrict the hwprobe calls to that set.
> >
> > Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> > ---
> > .../testing/selftests/riscv/hwprobe/Makefile | 7 +-
> > tools/testing/selftests/riscv/hwprobe/cbo.c | 162 ++++++++++++++++++
> > .../testing/selftests/riscv/hwprobe/hwprobe.c | 12 +-
> > .../testing/selftests/riscv/hwprobe/hwprobe.h | 15 ++
> > 4 files changed, 184 insertions(+), 12 deletions(-)
> > create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c
> > create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h
> >
> > diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile
> > b/tools/testing/selftests/riscv/hwprobe/Makefile
> > index 5f614c3ba598..f224b84591fb 100644
> > --- a/tools/testing/selftests/riscv/hwprobe/Makefile
> > +++ b/tools/testing/selftests/riscv/hwprobe/Makefile
> > @@ -2,9 +2,14 @@
> > # Copyright (C) 2021 ARM Limited
> > # Originally tools/testing/arm64/abi/Makefile
> >
> > -TEST_GEN_PROGS := hwprobe
> > +CFLAGS += -I$(top_srcdir)/tools/include
> > +
> > +TEST_GEN_PROGS := hwprobe cbo
> >
> > include ../../lib.mk
> >
> > $(OUTPUT)/hwprobe: hwprobe.c sys_hwprobe.S
> > $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
> > +
> > +$(OUTPUT)/cbo: cbo.c sys_hwprobe.S
> > + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
> > diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c
> > b/tools/testing/selftests/riscv/hwprobe/cbo.c
> > new file mode 100644
> > index 000000000000..920abfaa10c2
> > --- /dev/null
> > +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c
> > @@ -0,0 +1,162 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2023 Ventana Micro Systems Inc.
> > + *
> > + * Run with 'taskset -c <cpu-list> cbo' to only execute hwprobe on a
> > + * subset of cpus, as well as only executing the tests on those cpus.
> > + */
> > +#define _GNU_SOURCE
> > +#include <stdbool.h>
> > +#include <stdint.h>
> > +#include <sched.h>
> > +#include <signal.h>
> > +#include <assert.h>
> > +#include <linux/compiler.h>
> > +#include <asm/ucontext.h>
> > +
> > +#include "hwprobe.h"
> > +#include "../../kselftest.h"
> > +
> > +static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 };
> > +
> > +static bool illegal_insn;
> > +
> > +static void sigill_handler(int sig, siginfo_t *info, void *context)
> > +{
> > + unsigned long *regs = (unsigned long *)&((ucontext_t *)context)-
> > >uc_mcontext;
> > + uint32_t insn = *(uint32_t *)regs[0];
> > +
> > + assert(insn >> 20 == regs[11] &&
> > + (insn & ((1 << 20) - 1)) == (10 << 15 | 2 << 12 | 0 << 7 | 15));
> > +
> > + illegal_insn = true;
> > + regs[0] += 4;
> > +}
> > +
> > +static void cbo_insn(int fn, char *base)
> > +{
> > + asm volatile(
> > + "mv a0, %0\n"
> > + "li a1, %1\n"
> > + ".4byte %1 << 20 | 10 << 15 | 2 << 12 | 0 << 7 | 15\n"
> > + : : "r" (base), "i" (fn) : "a0", "a1", "memory");
> > +}
> > +
> > +static void cbo_inval(char *base) { cbo_insn(0, base); }
> > +static void cbo_clean(char *base) { cbo_insn(1, base); }
> > +static void cbo_flush(char *base) { cbo_insn(2, base); }
> > +static void cbo_zero(char *base) { cbo_insn(4, base); }
> > +
> > +static void test_no_zicbom(void)
> > +{
> > + illegal_insn = false;
> > + cbo_clean(&mem[0]);
> > + ksft_test_result(illegal_insn, "No cbo.clean\n");
> > +
> > + illegal_insn = false;
> > + cbo_flush(&mem[0]);
> > + ksft_test_result(illegal_insn, "No cbo.flush\n");
> > +
> > + illegal_insn = false;
> > + cbo_inval(&mem[0]);
> > + ksft_test_result(illegal_insn, "No cbo.inval\n");
> > +}
> > +
> > +static void test_no_zicboz(void)
> > +{
> > + illegal_insn = false;
> > + cbo_clean(&mem[0]);
>
> Seems we need to call cbo_zero() instead of cbo_clean().
Nice catch, Xiao. Copy+paste mistake... Will fix for v3.
Thanks,
drew
>
> BRs,
> Xiao
>
> > + ksft_test_result(illegal_insn, "No cbo.zero\n");
> > +}
> > +
> [...]
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2023-09-01 15:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-30 16:49 [PATCH v2 0/6] RISC-V: Enable cbo.zero in usermode Andrew Jones
2023-08-30 16:49 ` [PATCH v2 1/6] RISC-V: Make zicbom/zicboz errors consistent Andrew Jones
2023-08-30 16:49 ` [PATCH v2 2/6] RISC-V: Enable cbo.zero in usermode Andrew Jones
2023-08-31 16:24 ` Conor Dooley
2023-08-31 16:39 ` Andrew Jones
2023-08-31 16:46 ` Conor Dooley
2023-08-30 16:49 ` [PATCH v2 3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size Andrew Jones
2023-08-31 16:19 ` Conor Dooley
2023-08-30 16:49 ` [PATCH v2 4/6] RISC-V: selftests: Statically link hwprobe test Andrew Jones
2023-08-30 16:50 ` [PATCH v2 5/6] RISC-V: selftests: Convert hwprobe test to kselftest API Andrew Jones
2023-08-30 16:50 ` [PATCH v2 6/6] RISC-V: selftests: Add CBO tests Andrew Jones
2023-09-01 9:37 ` Wang, Xiao W
2023-09-01 15:12 ` Andrew Jones [this message]
2023-08-30 16:52 ` [PATCH v2 0/6] RISC-V: Enable cbo.zero in usermode Andrew Jones
2023-08-30 20:28 ` Palmer Dabbelt
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