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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id o4-20020a5d6844000000b003197b85bad2sm5540732wrw.79.2023.09.01.08.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Sep 2023 08:12:09 -0700 (PDT) Date: Fri, 1 Sep 2023 17:12:08 +0200 From: Andrew Jones To: "Wang, Xiao W" Cc: "linux-riscv@lists.infradead.org" , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "aou@eecs.berkeley.edu" , "evan@rivosinc.com" , "conor.dooley@microchip.com" , "apatel@ventanamicro.com" Subject: Re: [PATCH v2 6/6] RISC-V: selftests: Add CBO tests Message-ID: <20230901-b4e5f6219de94391e5fa11d6@orel> References: <20230830164954.91987-8-ajones@ventanamicro.com> <20230830164954.91987-14-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230901_081211_892289_2DF5F8C2 X-CRM114-Status: GOOD ( 30.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Sep 01, 2023 at 09:37:27AM +0000, Wang, Xiao W wrote: > Hi, > > > -----Original Message----- > > From: linux-riscv On Behalf Of > > Andrew Jones > > Sent: Thursday, August 31, 2023 12:50 AM > > To: linux-riscv@lists.infradead.org > > Cc: paul.walmsley@sifive.com; palmer@dabbelt.com; > > aou@eecs.berkeley.edu; evan@rivosinc.com; conor.dooley@microchip.com; > > apatel@ventanamicro.com > > Subject: [PATCH v2 6/6] RISC-V: selftests: Add CBO tests > > > > Add hwprobe test for Zicboz and its block size. Also, when Zicboz is > > present, test that cbo.zero may be issued and works. Additionally > > test that the Zicbom instructions cause SIGILL and also that cbo.zero > > causes SIGILL when Zicboz is not present. Pinning the test to a subset > > of cpus with taskset will also restrict the hwprobe calls to that set. > > > > Signed-off-by: Andrew Jones > > --- > > .../testing/selftests/riscv/hwprobe/Makefile | 7 +- > > tools/testing/selftests/riscv/hwprobe/cbo.c | 162 ++++++++++++++++++ > > .../testing/selftests/riscv/hwprobe/hwprobe.c | 12 +- > > .../testing/selftests/riscv/hwprobe/hwprobe.h | 15 ++ > > 4 files changed, 184 insertions(+), 12 deletions(-) > > create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c > > create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h > > > > diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile > > b/tools/testing/selftests/riscv/hwprobe/Makefile > > index 5f614c3ba598..f224b84591fb 100644 > > --- a/tools/testing/selftests/riscv/hwprobe/Makefile > > +++ b/tools/testing/selftests/riscv/hwprobe/Makefile > > @@ -2,9 +2,14 @@ > > # Copyright (C) 2021 ARM Limited > > # Originally tools/testing/arm64/abi/Makefile > > > > -TEST_GEN_PROGS := hwprobe > > +CFLAGS += -I$(top_srcdir)/tools/include > > + > > +TEST_GEN_PROGS := hwprobe cbo > > > > include ../../lib.mk > > > > $(OUTPUT)/hwprobe: hwprobe.c sys_hwprobe.S > > $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ > > + > > +$(OUTPUT)/cbo: cbo.c sys_hwprobe.S > > + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ > > diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c > > b/tools/testing/selftests/riscv/hwprobe/cbo.c > > new file mode 100644 > > index 000000000000..920abfaa10c2 > > --- /dev/null > > +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c > > @@ -0,0 +1,162 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Copyright (c) 2023 Ventana Micro Systems Inc. > > + * > > + * Run with 'taskset -c cbo' to only execute hwprobe on a > > + * subset of cpus, as well as only executing the tests on those cpus. > > + */ > > +#define _GNU_SOURCE > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "hwprobe.h" > > +#include "../../kselftest.h" > > + > > +static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 }; > > + > > +static bool illegal_insn; > > + > > +static void sigill_handler(int sig, siginfo_t *info, void *context) > > +{ > > + unsigned long *regs = (unsigned long *)&((ucontext_t *)context)- > > >uc_mcontext; > > + uint32_t insn = *(uint32_t *)regs[0]; > > + > > + assert(insn >> 20 == regs[11] && > > + (insn & ((1 << 20) - 1)) == (10 << 15 | 2 << 12 | 0 << 7 | 15)); > > + > > + illegal_insn = true; > > + regs[0] += 4; > > +} > > + > > +static void cbo_insn(int fn, char *base) > > +{ > > + asm volatile( > > + "mv a0, %0\n" > > + "li a1, %1\n" > > + ".4byte %1 << 20 | 10 << 15 | 2 << 12 | 0 << 7 | 15\n" > > + : : "r" (base), "i" (fn) : "a0", "a1", "memory"); > > +} > > + > > +static void cbo_inval(char *base) { cbo_insn(0, base); } > > +static void cbo_clean(char *base) { cbo_insn(1, base); } > > +static void cbo_flush(char *base) { cbo_insn(2, base); } > > +static void cbo_zero(char *base) { cbo_insn(4, base); } > > + > > +static void test_no_zicbom(void) > > +{ > > + illegal_insn = false; > > + cbo_clean(&mem[0]); > > + ksft_test_result(illegal_insn, "No cbo.clean\n"); > > + > > + illegal_insn = false; > > + cbo_flush(&mem[0]); > > + ksft_test_result(illegal_insn, "No cbo.flush\n"); > > + > > + illegal_insn = false; > > + cbo_inval(&mem[0]); > > + ksft_test_result(illegal_insn, "No cbo.inval\n"); > > +} > > + > > +static void test_no_zicboz(void) > > +{ > > + illegal_insn = false; > > + cbo_clean(&mem[0]); > > Seems we need to call cbo_zero() instead of cbo_clean(). Nice catch, Xiao. Copy+paste mistake... Will fix for v3. Thanks, drew > > BRs, > Xiao > > > + ksft_test_result(illegal_insn, "No cbo.zero\n"); > > +} > > + > [...] > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv