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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id d9-20020a5d4f89000000b0031c5b380291sm18421408wru.110.2023.09.05.13.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Sep 2023 13:18:32 -0700 (PDT) Date: Tue, 5 Sep 2023 22:18:31 +0200 From: Andrew Jones To: "Wang, Xiao W" Cc: "linux-riscv@lists.infradead.org" , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "aou@eecs.berkeley.edu" , "evan@rivosinc.com" , "conor.dooley@microchip.com" , "apatel@ventanamicro.com" Subject: Re: [PATCH v3 6/6] RISC-V: selftests: Add CBO tests Message-ID: <20230905-b49ac6791300beb8845ba196@orel> References: <20230904170220.167816-8-ajones@ventanamicro.com> <20230904170220.167816-14-ajones@ventanamicro.com> <20230905-1ca92f76cd928ff3f6e51c71@orel> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230905-1ca92f76cd928ff3f6e51c71@orel> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230905_131837_232027_6FEAB2B2 X-CRM114-Status: GOOD ( 18.59 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Sep 05, 2023 at 06:10:25PM +0200, Andrew Jones wrote: > On Tue, Sep 05, 2023 at 02:36:44PM +0000, Wang, Xiao W wrote: > > Hi, > > > > > -----Original Message----- > > > From: linux-riscv On Behalf Of > > > Andrew Jones ... > > > +#define MK_CBO(fn) ((fn) << 20 | 10 << 15 | 2 << 12 | 0 << 7 | 15) > > > + > > > +static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 }; > > > + > > > +static bool illegal_insn; > > > + > > > +static void sigill_handler(int sig, siginfo_t *info, void *context) > > > +{ > > > + unsigned long *regs = (unsigned long *)&((ucontext_t *)context)- > > > >uc_mcontext; > > > + uint32_t insn = *(uint32_t *)regs[0]; > > > + > > > + assert(insn == MK_CBO(regs[11])); > > > > > > The byte order of insn should always be little endian, while the CPU may be a big-endian one, then the check might fail. > > Maybe we can use __le32_to_cpu(insn) to convert it before the check. > > Sounds good (minus the leading __, since we don't have __le32_to_cpu() in > tools). > Actually, don't I also need to ensure byte order when creating the instruction in cbo_insn() with ".4byte %2" where %2 is insn which is MK_CBO(fn)? I presume so, which means the proper fix would be to add a cpu_to_le32() to MK_CBO(), i.e. #define MK_CBO(fn) cpu_to_le32((fn) << 20 | 10 << 15 | 2 << 12 | 0 << 7 | 15) Unless somebody tells me otherwise, then I'll do that for v4. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv