Re: [PATCH] RISC-V: Optimize bitops with Zbb extension

[Andrew Jones <ajones@ventanamicro.com>]

Hi Xiao,

On Tue, Sep 05, 2023 at 09:46:20AM +0000, Wang, Xiao W wrote:
> 
> 
> > -----Original Message-----
> > From: Andrew Jones <ajones@ventanamicro.com>
> > Sent: Friday, September 1, 2023 1:00 AM
> > To: Anup Patel <apatel@ventanamicro.com>
> > Cc: Wang, Xiao W <xiao.w.wang@intel.com>; Conor Dooley
> > <conor.dooley@microchip.com>; Anup Patel <anup@brainfault.org>;
> > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> > ardb@kernel.org; Li, Haicheng <haicheng.li@intel.com>; linux-
> > riscv@lists.infradead.org; linux-efi@vger.kernel.org; linux-
> > kernel@vger.kernel.org
> > Subject: Re: [PATCH] RISC-V: Optimize bitops with Zbb extension
> > 
> > On Thu, Aug 31, 2023 at 09:37:30PM +0530, Anup Patel wrote:
> > > +Andrew
> > >
> > > On Thu, Aug 31, 2023 at 9:29 PM Wang, Xiao W <xiao.w.wang@intel.com>
> > wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Conor Dooley <conor.dooley@microchip.com>
> > > > > Sent: Wednesday, August 30, 2023 2:59 PM
> > > > > To: Wang, Xiao W <xiao.w.wang@intel.com>
> > > > > Cc: Anup Patel <anup@brainfault.org>; paul.walmsley@sifive.com;
> > > > > palmer@dabbelt.com; aou@eecs.berkeley.edu; ardb@kernel.org; Li,
> > Haicheng
> > > > > <haicheng.li@intel.com>; linux-riscv@lists.infradead.org; linux-
> > > > > efi@vger.kernel.org; linux-kernel@vger.kernel.org
> > > > > Subject: Re: [PATCH] RISC-V: Optimize bitops with Zbb extension
> > > > >
> > > > > On Wed, Aug 30, 2023 at 06:14:12AM +0000, Wang, Xiao W wrote:
> > > > > > Hi,
> > > > > >
> > > > > > > -----Original Message-----
> > > > > > > From: Anup Patel <anup@brainfault.org>
> > > > > > > Sent: Tuesday, August 29, 2023 7:08 PM
> > > > > > > To: Wang, Xiao W <xiao.w.wang@intel.com>
> > > > > > > Cc: paul.walmsley@sifive.com; palmer@dabbelt.com;
> > > > > > > aou@eecs.berkeley.edu; ardb@kernel.org; Li, Haicheng
> > > > > > > <haicheng.li@intel.com>; linux-riscv@lists.infradead.org; linux-
> > > > > > > efi@vger.kernel.org; linux-kernel@vger.kernel.org
> > > > > > > Subject: Re: [PATCH] RISC-V: Optimize bitops with Zbb extension
> > > > > > >
> > > > > > > On Sun, Aug 6, 2023 at 8:09 AM Xiao Wang
> > <xiao.w.wang@intel.com>
> > > > > wrote:
> > > > > > > >
> > > > > > > > This patch leverages the alternative mechanism to dynamically
> > optimize
> > > > > > > > bitops (including __ffs, __fls, ffs, fls) with Zbb instructions. When
> > > > > > > > Zbb ext is not supported by the runtime CPU, legacy implementation
> > is
> > > > > > > > used. If Zbb is supported, then the optimized variants will be
> > selected
> > > > > > > > via alternative patching.
> > > > > > > >
> > > > > > > > The legacy bitops support is taken from the generic C
> > implementation as
> > > > > > > > fallback.
> > > > > > > >
> > > > > > > > If the parameter is a build-time constant, we leverage compiler
> > builtin to
> > > > > > > > calculate the result directly, this approach is inspired by x86 bitops
> > > > > > > > implementation.
> > > > > > > >
> > > > > > > > EFI stub runs before the kernel, so alternative mechanism should not
> > be
> > > > > > > > used there, this patch introduces a macro EFI_NO_ALTERNATIVE for
> > this
> > > > > > > > purpose.
> > > > > > >
> > > > > > > I am getting the following compile error with this patch:
> > > > > > >
> > > > > > >   GEN     Makefile
> > > > > > >   UPD     include/config/kernel.release
> > > > > > >   UPD     include/generated/utsrelease.h
> > > > > > >   CC      kernel/bounds.s
> > > > > > > In file included from /home/anup/Work/riscv-
> > > > > > > test/linux/include/linux/bitmap.h:9,
> > > > > > >                  from
> > > > > > > /home/anup/Work/riscv-
> > > > > test/linux/arch/riscv/include/asm/cpufeature.h:9,
> > > > > > >                  from
> > > > > > > /home/anup/Work/riscv-
> > test/linux/arch/riscv/include/asm/hwcap.h:90,
> > > > > >
> > > > > >
> > > > > > It looks there's a cyclic header including, which leads to this build error.
> > > > > > I checked https://github.com/kvm-riscv/linux/tree/master and
> > > > > > https://github.com/torvalds/linux/tree/master, but I don't see
> > > > > > "asm/cpufeature.h" is included in asm/hwcap.h:90, maybe I miss
> > > > > something,
> > > > > > could you help point me to the repo/branch I should work on?
> > > > >
> > > > > From MAINTAINERS:
> > > > >       RISC-V ARCHITECTURE
> > > > >       ...
> > > > >       T:      git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
> > > > >
> > > > > The for-next branch there is what you should be basing work on top of.
> > > > > AFAICT, you've made bitops.h include hwcap.h while cpufeature.h
> > includes
> > > > > both bitops.h (indirectly) and hwcap.h.
> > > >
> > > > Thanks for the info, but I can't reproduce Anup's build error with this for-
> > next branch, cpufeature.h is not included by hwcap.h there.
> > > > Maybe Anup could help double check the test environment?
> > >
> > > I figured that cpufeature.h included in hwcap.h is added by
> > > Drew's patch "RISC-V: Enable cbo.zero in usermode"
> > 
> > I think we should probably split hwcap.h into two parts. The defines stay
> > and the rest can move to cpufeature.h
> 
> OK, I will base on your cbo.zero enabling patch series to make a new version. Will move some contents from hwcap.h into cpufeature.h so that we can remove the including of cpufeature.h in hwcap.h.
> 

I just realized I forgot to CC you on my v3 posting of the cbo.zero
series[1] yesterday. Sorry about that.

[1] https://lore.kernel.org/all/20230904170220.167816-8-ajones@ventanamicro.com/

Thanks,
drew

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