From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
Heiko Stuebner <heiko@sntech.de>,
Drew Fustini <dfustini@baylibre.com>,
linux-kernel@vger.kernel.org, Guo Ren <guoren@kernel.org>,
linux-riscv@lists.infradead.org
Subject: [PATCH v3] riscv: errata: fix T-Head dcache.cva encoding
Date: Tue, 12 Sep 2023 15:24:10 +0800 [thread overview]
Message-ID: <20230912072410.2481-1-jszhang@kernel.org> (raw)
From: Icenowy Zheng <uwu@icenowy.me>
The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.
Fix this in the comment and in the hardcoded instruction.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
---
This is a renew of Icenowy patch series[1], patch1 is necessary to
make T-Head C910 powered SoCs CMO work correctly.
Link: https://lore.kernel.org/linux-riscv/20230103062610.69704-1-uwu@icenowy.me/ [1]
Since v2:
- rebase on linux 6.6-rc1
- collect Tested-by tag
- remove patch2 since I want patch1 to be applied as fix for
linux-6.6. patch2 will be sent separately.
Since v1:
- rebase on linux 6.5-rc7
- collect Reviewed-by tag
arch/riscv/include/asm/errata_list.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index e2ecd01bfac7..b55b434f0059 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -105,7 +105,7 @@ asm volatile(ALTERNATIVE( \
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01001 rs1 000 00000 0001011
* dcache.cva rs1 (clean, virtual address)
- * 0000001 00100 rs1 000 00000 0001011
+ * 0000001 00101 rs1 000 00000 0001011
*
* dcache.cipa rs1 (clean then invalidate, physical address)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -118,7 +118,7 @@ asm volatile(ALTERNATIVE( \
* 0000000 11001 00000 000 00000 0001011
*/
#define THEAD_inval_A0 ".long 0x0265000b"
-#define THEAD_clean_A0 ".long 0x0245000b"
+#define THEAD_clean_A0 ".long 0x0255000b"
#define THEAD_flush_A0 ".long 0x0275000b"
#define THEAD_SYNC_S ".long 0x0190000b"
--
2.40.1
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next reply other threads:[~2023-09-12 7:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 7:24 Jisheng Zhang [this message]
2023-09-13 0:23 ` [PATCH v3] riscv: errata: fix T-Head dcache.cva encoding Palmer Dabbelt
2023-09-13 0:37 ` patchwork-bot+linux-riscv
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