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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id r8-20020a5d4e48000000b0031ad2f9269dsm1137143wrt.40.2023.09.14.01.52.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 01:52:14 -0700 (PDT) Date: Thu, 14 Sep 2023 10:52:08 +0200 From: Andrew Jones To: Haibo Xu Cc: xiaobo55x@gmail.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Sean Christopherson , Ricardo Koller , Vishal Annapurve , Peter Xu , Vipin Sharma , David Matlack , Colton Lewis , Aaron Lewis , Thomas Huth , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v3 5/9] KVM: riscv: selftests: Switch to use macro from csr.h Message-ID: <20230914-18bfe93b679e290188e70307@orel> References: <6cdda82518977c67004ee01a767bc67962352c13.1694421911.git.haibo1.xu@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <6cdda82518977c67004ee01a767bc67962352c13.1694421911.git.haibo1.xu@intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230914_015219_314712_E04EA18C X-CRM114-Status: GOOD ( 14.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Sep 14, 2023 at 09:36:59AM +0800, Haibo Xu wrote: > Signed-off-by: Haibo Xu > --- > tools/testing/selftests/kvm/include/riscv/processor.h | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h > index 5b62a3d2aa9b..67766baed4f7 100644 > --- a/tools/testing/selftests/kvm/include/riscv/processor.h > +++ b/tools/testing/selftests/kvm/include/riscv/processor.h > @@ -8,6 +8,7 @@ > #define SELFTEST_KVM_PROCESSOR_H > > #include "kvm_util.h" > +#include > #include nit: Usually we try to keep the order of our includes separated into five categories, listed below, where each category is sorted alphabetically. Of course any dependencies the includes have on each other need to be considered too. "local-includes" > > static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, > @@ -95,13 +96,6 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, > #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE > #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT > > -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) > -#define SATP_MODE_39 _AC(0x8000000000000000, UL) > -#define SATP_MODE_48 _AC(0x9000000000000000, UL) > -#define SATP_ASID_BITS 16 > -#define SATP_ASID_SHIFT 44 > -#define SATP_ASID_MASK _AC(0xFFFF, UL) > - > #define SBI_EXT_EXPERIMENTAL_START 0x08000000 > #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF > > -- > 2.34.1 > Assuming the CONFIG_64BIT patch will come before this, then Reviewed-by: Andrew Jones Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv