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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id f7-20020adff987000000b0031c8a43712asm1914525wrr.69.2023.09.14.07.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 07:25:59 -0700 (PDT) Date: Thu, 14 Sep 2023 16:25:53 +0200 From: Andrew Jones To: guoren@kernel.org Cc: paul.walmsley@sifive.com, anup@brainfault.org, peterz@infradead.org, mingo@redhat.com, will@kernel.org, palmer@rivosinc.com, longman@redhat.com, boqun.feng@gmail.com, tglx@linutronix.de, paulmck@kernel.org, rostedt@goodmis.org, rdunlap@infradead.org, catalin.marinas@arm.com, conor.dooley@microchip.com, xiaoguang.xing@sophgo.com, bjorn@rivosinc.com, alexghiti@rivosinc.com, keescook@chromium.org, greentime.hu@sifive.com, jszhang@kernel.org, wefu@redhat.com, wuwei2016@iscas.ac.cn, leobras@redhat.com, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, virtualization@lists.linux-foundation.org, linux-csky@vger.kernel.org, Guo Ren Subject: Re: [PATCH V11 03/17] riscv: Use Zicbop in arch_xchg when available Message-ID: <20230914-892327a75b4b86badac5de02@orel> References: <20230910082911.3378782-1-guoren@kernel.org> <20230910082911.3378782-4-guoren@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230910082911.3378782-4-guoren@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230914_072603_904046_AB016D26 X-CRM114-Status: GOOD ( 19.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Sep 10, 2023 at 04:28:57AM -0400, guoren@kernel.org wrote: > From: Guo Ren > > Cache-block prefetch instructions are HINTs to the hardware to > indicate that software intends to perform a particular type of > memory access in the near future. Enable ARCH_HAS_PREFETCHW and > improve the arch_xchg for qspinlock xchg_tail. > > Signed-off-by: Guo Ren > Signed-off-by: Guo Ren > --- > arch/riscv/Kconfig | 15 +++++++++++++++ > arch/riscv/include/asm/cmpxchg.h | 4 +++- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/insn-def.h | 5 +++++ > arch/riscv/include/asm/processor.h | 13 +++++++++++++ > arch/riscv/kernel/cpufeature.c | 1 + > 6 files changed, 38 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index e9ae6fa232c3..2c346fe169c1 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -617,6 +617,21 @@ config RISCV_ISA_ZICBOZ > > If you don't know what to do here, say Y. > > +config RISCV_ISA_ZICBOP Even if we're not concerned with looping over blocks yet, I think we should introduce zicbop block size DT parsing at the same time we bring zicbop support to the kernel (it's just more copy+paste from zicbom and zicboz). It's a bit annoying that the CMO spec doesn't state that block sizes should be the same for m/z/p. And, the fact that m/z/p are all separate extensions leads us to needing to parse block sizes for all three, despite the fact that in practice they'll probably be the same. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv