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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id p6-20020a7bcc86000000b003fbdbd0a7desm4074945wma.27.2023.09.14.01.14.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 01:14:06 -0700 (PDT) Date: Thu, 14 Sep 2023 10:14:05 +0200 From: Andrew Jones To: Haibo Xu Cc: xiaobo55x@gmail.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Sean Christopherson , Ricardo Koller , Vishal Annapurve , Vipin Sharma , David Matlack , Thomas Huth , Aaron Lewis , Colton Lewis , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v3 4/9] tools: riscv: Add header file csr.h Message-ID: <20230914-90a562a03985a9a97afd953a@orel> References: <119c9d06d64b7e4932c5f74a05af1e769cbe7da6.1694421911.git.haibo1.xu@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <119c9d06d64b7e4932c5f74a05af1e769cbe7da6.1694421911.git.haibo1.xu@intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230914_011411_112796_30794D0D X-CRM114-Status: GOOD ( 17.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Sep 14, 2023 at 09:36:58AM +0800, Haibo Xu wrote: > Borrow the csr definitions and operations from kernel's > arch/riscv/include/asm/csr.h to tools/ for riscv. Since > only 64bit was supported for RISC-V KVM selftests, add > CONFIG_64BIT definition in kvm/Makefile to ensure only > 64bit registers were available in csr.h. > > Suggested-by: Andrew Jones > Signed-off-by: Haibo Xu > Reviewed-by: Andrew Jones > --- > tools/arch/riscv/include/asm/csr.h | 521 +++++++++++++++++++++++++++ > tools/testing/selftests/kvm/Makefile | 3 + > 2 files changed, 524 insertions(+) > create mode 100644 tools/arch/riscv/include/asm/csr.h > > diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h > new file mode 100644 > index 000000000000..4e86c82aacbd > --- /dev/null > +++ b/tools/arch/riscv/include/asm/csr.h ... > diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile > index 0102a0297b84..89ecee2fdb73 100644 > --- a/tools/testing/selftests/kvm/Makefile > +++ b/tools/testing/selftests/kvm/Makefile > @@ -222,6 +222,9 @@ CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \ > ifeq ($(ARCH),s390) > CFLAGS += -march=z10 > endif > +ifeq ($(ARCH),riscv) > + CFLAGS += -DCONFIG_64BIT > +endif This should be a separate patch, since the "import csr.h to tools" should be completely separate from anything else. Also, all architectures that KVM selftests supports are 64-bit, so, as another completely separate patch, I think we should just add CONFIG_64BIT to CFLAGS for all builds, especially since there's a chance some of the includes the other architectures are using may need it. Of course we'll need sign-off and testing from the other arch maintainers. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv