From: Conor Dooley <conor.dooley@microchip.com>
To: "Björn Töpel" <bjorn@kernel.org>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org,
"Andy Chiu" <andy.chiu@sifive.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Jason A . Donenfeld" <Jason@zx2c4.com>,
"Samuel Neves" <sneves@dei.uc.pt>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Herbert Xu" <herbert@gondor.apana.org.au>,
"David S. Miller" <davem@davemloft.net>,
linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 6/6] riscv: Add BLAKE2s V implementation
Date: Thu, 14 Sep 2023 13:52:34 +0100 [thread overview]
Message-ID: <20230914-charting-detector-3d2b615393b9@wendy> (raw)
In-Reply-To: <20230912115728.172982-7-bjorn@kernel.org>
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On Tue, Sep 12, 2023 at 01:57:28PM +0200, Björn Töpel wrote:
> From: Björn Töpel <bjorn@rivosinc.com>
>
> BLAKE2s is used in various places, most notably in Wireguard, and as
> of v5.17 in drivers/char/random.
>
> Add a BLAKE2s implementation using the V-extension. This is a
> translation of the x86-64 AVX512 variant
> (arch/x86/crypto/blake2s-core.S) to the RISC-V V-extension.
>
> The AVX512 variant requires registers >= 256b (ymm*), and hence this
> implementation requires a VLEN of >=256.
>
> The implementation passes the kernel BLAKE2s selftest, and has been
> tested on spike and qemu.
>
> Instruction-wise, the V-variant uses 60% less instructions than the
> generic, C-based, implementation.
>
> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
> arch/riscv/crypto/blake2s-v.S | 164 +++++++++++++++++++++++++++++++
This file is currently being built for !RISCV_ISA_V, leading to build errors
for obvious reasons. Eg:
../arch/riscv/crypto/blake2s-v.S:62:2: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
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next prev parent reply other threads:[~2023-09-14 12:53 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 11:57 [RFC PATCH 0/6] RISC-V BLAKE2s Vector implementation Björn Töpel
2023-09-12 11:57 ` [RFC PATCH 1/6] riscv: sched: defer restoring Vector context for user Björn Töpel
2023-09-12 11:57 ` [RFC PATCH 2/6] riscv: Add support for kernel mode vector Björn Töpel
2023-09-12 11:57 ` [RFC PATCH 3/6] riscv: Add vector extension XOR implementation Björn Töpel
2023-09-12 11:57 ` [RFC PATCH 4/6] riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}() Björn Töpel
2023-09-12 11:57 ` [RFC PATCH 5/6] riscv: vector: allow kernel-mode Vector with preemption Björn Töpel
2023-09-12 11:57 ` [RFC PATCH 6/6] riscv: Add BLAKE2s V implementation Björn Töpel
2023-09-14 12:52 ` Conor Dooley [this message]
2023-09-14 12:57 ` Björn Töpel
2023-09-15 18:29 ` Charlie Jenkins
2023-09-21 5:57 ` Björn Töpel
2023-09-14 12:49 ` [RFC PATCH 0/6] RISC-V BLAKE2s Vector implementation Conor Dooley
2023-09-14 12:59 ` Björn Töpel
2023-09-14 13:05 ` Conor Dooley
2023-09-14 14:15 ` Björn Töpel
2023-09-14 14:18 ` Conor Dooley
2023-09-14 14:24 ` Andy Chiu
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