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b=Aot5xG/6zIolsjLGE5BJmtgsqhht4rr+me+2ndd8awnkztVbNhAiLAvvsME7T59k+ ouRa5EjpKsSiMqOfu4anPN+YLXYZS8GiuNVwRqGMMD1OFinsUUn/vO99YLghxFT/GX J5LRTFmw+yyemnwpFV9q4rzR4yA8b1KoDXUiLhO///f7jPZaiCjfx9vPJf+sdmwBCN ZunHALiK4sZKZmvJfO2pCw9BqLXTKETuaXYX3s+giP4i8tgy11zPmrNH/1JkvgiES4 d+TNqqCfrrtawHn759zJpSAfW5zmH98hjcV96BpnV3A9TOxik/0n7uJGaAd3Dbskve H+BQwEJghQsBw== Date: Fri, 15 Sep 2023 15:11:43 +0100 From: Conor Dooley To: Wang Chen Cc: linux-riscv@lists.infradead.org, aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, Wang Chen Subject: Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles Message-ID: <20230915-muster-viability-93d7d4ec2b49@spud> References: <20230915072333.117991-1-wangchen20@iscas.ac.cn> MIME-Version: 1.0 In-Reply-To: <20230915072333.117991-1-wangchen20@iscas.ac.cn> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230915_071153_178690_FB0997FE X-CRM114-Status: GOOD ( 15.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8050258628535142870==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============8050258628535142870== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="53Jv7XerkC9sk4oP" Content-Disposition: inline --53Jv7XerkC9sk4oP Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote: > The C920 is RISC-V CPU cores from T-HEAD Semiconductor. > Notably, the C920 core is used in the SOPHGO SG2042 SoC. >=20 > Signed-off-by: Wang Chen > Signed-off-by: Xiaoguang Xing I figure this is missing a From: or Co-developed-by line. > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Document= ation/devicetree/bindings/riscv/cpus.yaml > index 38c0b5213736..185a0191bad6 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -47,6 +47,7 @@ properties: > - sifive,u74-mc > - thead,c906 > - thead,c910 > + - thead,c920 > - const: riscv > - items: > - enum: > --=20 > 2.25.1 >=20 --53Jv7XerkC9sk4oP Content-Type: application/pgp-signature; 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