From: Conor Dooley <conor@kernel.org>
To: Evan Green <evan@rivosinc.com>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Heiko Stuebner <heiko@sntech.de>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>,
David Laight <David.Laight@aculab.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Jisheng Zhang <jszhang@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greentime Hu <greentime.hu@sifive.com>,
linux-riscv@lists.infradead.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH] RISC-V: Probe misaligned access speed in parallel
Date: Sat, 16 Sep 2023 01:16:30 +0100 [thread overview]
Message-ID: <20230916-celtic-flavored-f6e5f49cec20@spud> (raw)
In-Reply-To: <20230915184904.1976183-1-evan@rivosinc.com>
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Yo Evan,
On Fri, Sep 15, 2023 at 11:49:03AM -0700, Evan Green wrote:
> Probing for misaligned access speed takes about 0.06 seconds. On a
> system with 64 cores, doing this in smp_callin() means it's done
> serially, extending boot time by 3.8 seconds. That's a lot of boot time.
>
> Instead of measuring each CPU serially, let's do the measurements on
> all CPUs in parallel. If we disable preemption on all CPUs, the
> jiffies stop ticking, so we can do this in stages of 1) everybody
> except core 0, then 2) core 0.
>
> The measurement call in smp_callin() stays around, but is now
> conditionalized to only run if a new CPU shows up after the round of
> in-parallel measurements has run. The goal is to have the measurement
> call not run during boot or suspend/resume, but only on a hotplug
> addition.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
>
> ---
>
> Jisheng, I didn't add your Tested-by tag since the patch evolved from
> the one you tested. Hopefully this one brings you the same result.
Ya know, I think there's scope to add Reported-by:, Closes: and Fixes:
tags to this patch, mentioning explicitly that this has regressed boot
time for many core systems, so that this can be fixes material. What do
you think?
> ---
> arch/riscv/include/asm/cpufeature.h | 3 ++-
> arch/riscv/kernel/cpufeature.c | 28 +++++++++++++++++++++++-----
> arch/riscv/kernel/smpboot.c | 11 ++++++++++-
> 3 files changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index d0345bd659c9..19e7817eba10 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -30,6 +30,7 @@ DECLARE_PER_CPU(long, misaligned_access_speed);
> /* Per-cpu ISA extensions. */
> extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> -void check_unaligned_access(int cpu);
> +extern bool misaligned_speed_measured;
> +int check_unaligned_access(void *unused);
>
> #endif
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1cfbba65d11a..8eb36e1dfb95 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -42,6 +42,9 @@ struct riscv_isainfo hart_isa[NR_CPUS];
> /* Performance information */
> DEFINE_PER_CPU(long, misaligned_access_speed);
>
> +/* Boot-time in-parallel unaligned access measurement has occurred. */
> +bool misaligned_speed_measured;
If you did something like s/measured/complete/ I think you could drop
the comment. Tis whatever though :)
Conor.
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next prev parent reply other threads:[~2023-09-16 0:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-15 18:49 [PATCH] RISC-V: Probe misaligned access speed in parallel Evan Green
2023-09-16 0:16 ` Conor Dooley [this message]
2023-09-16 6:45 ` Andrew Jones
2023-09-16 8:39 ` Jisheng Zhang
2023-11-01 11:31 ` Jisheng Zhang
2023-11-01 17:28 ` Evan Green
2023-11-02 17:07 ` Jisheng Zhang
2023-11-02 22:41 ` Evan Green
2023-11-03 8:34 ` Conor Dooley
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