[PATCH v4 0/6] RISC-V: Enable cbo.zero in usermode

[Andrew Jones <ajones@ventanamicro.com>]

In order for usermode to issue cbo.zero, it needs privilege granted to
issue the extension instruction (patch 2) and to know that the extension
is available and its block size (patch 3). Patch 1 could be separate from
this series (it just fixes up some error messages), patches 4-5 convert
the hwprobe selftest to a statically-linked, TAP test and patch 6 adds a
new hwprobe test for the new information as well as testing CBO
instructions can or cannot be issued as appropriate.

Thanks,
drew

v4:
  - All changes are in the last patch, the CBO selftest.
    - Ensure instruction encoding is LE [Xiao]
    - When Zicboz is reported not present, make sure none of the harts
      report it present [Xiao]
    - Only test for SIGILL when '--sigill' is given on the command line
      since not all platforms will issue sigill [Palmer]
    - Use hwprobe's 3rd argument, "cpu_count", properly. It's not
      CPU_COUNT, it's "cpusetsize"
    - Code organization changes

v3:
  - rebased on for-next
  - Explained the use of CONFIG_RISCV_ALTERNATIVE in the commit message
    for patch 2
  - fixed a copy+paste error in the cbo selftest [Xiao]
  - while touching the cbo selftest improved its readability with a
    MK_CBO() macro and now skip the cbo.zero test if we see the first
    try is an illegal instruction
  - picked up a few r-b's

v2:
  - fixed build of the vector selftest
  - changed this-cpu wrappers to just cpu wrappers and then pass
    smp_processor_id() at the callsite
  - added comment to EXT_KEY macro
  - picked up a couple r-b's


Andrew Jones (6):
  RISC-V: Make zicbom/zicboz errors consistent
  RISC-V: Enable cbo.zero in usermode
  RISC-V: hwprobe: Expose Zicboz extension and its block size
  RISC-V: selftests: Statically link hwprobe test
  RISC-V: selftests: Convert hwprobe test to kselftest API
  RISC-V: selftests: Add CBO tests

 Documentation/riscv/hwprobe.rst               |   6 +
 arch/riscv/include/asm/cpufeature.h           |   1 +
 arch/riscv/include/asm/csr.h                  |   1 +
 arch/riscv/include/asm/hwcap.h                |  16 ++
 arch/riscv/include/asm/hwprobe.h              |   2 +-
 arch/riscv/include/uapi/asm/hwprobe.h         |   2 +
 arch/riscv/kernel/cpufeature.c                |  10 +-
 arch/riscv/kernel/setup.c                     |   4 +
 arch/riscv/kernel/smpboot.c                   |   4 +
 arch/riscv/kernel/sys_riscv.c                 |  46 ++--
 .../testing/selftests/riscv/hwprobe/Makefile  |   9 +-
 tools/testing/selftests/riscv/hwprobe/cbo.c   | 228 ++++++++++++++++++
 .../testing/selftests/riscv/hwprobe/hwprobe.c |  64 ++---
 .../testing/selftests/riscv/hwprobe/hwprobe.h |  15 ++
 14 files changed, 345 insertions(+), 63 deletions(-)
 create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c
 create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h

-- 
2.41.0


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