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From: Andrew Jones <ajones@ventanamicro.com>
To: Xiao Wang <xiao.w.wang@intel.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu,  ardb@kernel.org, anup@brainfault.org,
	haicheng.li@intel.com,  linux-riscv@lists.infradead.org,
	linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h
Date: Wed, 20 Sep 2023 10:29:05 +0200	[thread overview]
Message-ID: <20230920-645cd4e9612d83768e596514@orel> (raw)
In-Reply-To: <20230920074653.2509631-2-xiao.w.wang@intel.com>

On Wed, Sep 20, 2023 at 03:46:52PM +0800, Xiao Wang wrote:
> Now hwcap.h and cpufeature.h are mutually including each other, and most of
> the variable/API declarations in hwcap.h are implemented in cpufeature.c,
> so, it's better to move them into cpufeature.h and leave only macros for
> ISA extension logical IDs in hwcap.h.
> 
> BTW, the riscv_isa_extension_mask macro is not used now, so this patch
> removes it.
> 
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>


Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew

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  reply	other threads:[~2023-09-20  8:29 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-20  7:46 [PATCH v2 0/2] riscv: Optimize bitops with Zbb extension Xiao Wang
2023-09-20  7:46 ` [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h Xiao Wang
2023-09-20  8:29   ` Andrew Jones [this message]
2023-09-26  6:18   ` kernel test robot
2023-09-26  8:39     ` Wang, Xiao W
2023-09-20  7:46 ` [PATCH v2 2/2] riscv: Optimize bitops with Zbb extension Xiao Wang

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