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boundary="===============5388628801499619915==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============5388628801499619915== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="BiR7UZp5nLCqNrq7" Content-Disposition: inline --BiR7UZp5nLCqNrq7 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Sep 20, 2023 at 02:38:08PM +0800, Chen Wang wrote: > The C920 is RISC-V CPU cores from T-HEAD Semiconductor. > Notably, the C920 core is used in the SOPHGO SG2042 SoC. >=20 > Acked-by: Xiaoguang Xing > Signed-off-by: Chen Wang Reviewed-by: Conor Dooley Thanks, Conor. > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Document= ation/devicetree/bindings/riscv/cpus.yaml > index 38c0b5213736..185a0191bad6 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -47,6 +47,7 @@ properties: > - sifive,u74-mc > - thead,c906 > - thead,c910 > + - thead,c920 > - const: riscv > - items: > - enum: > --=20 > 2.25.1 >=20 --BiR7UZp5nLCqNrq7 Content-Type: application/pgp-signature; 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