* [PATCH v2 0/2] riscv: Optimize bitops with Zbb extension @ 2023-09-20 7:46 Xiao Wang 2023-09-20 7:46 ` [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h Xiao Wang 2023-09-20 7:46 ` [PATCH v2 2/2] riscv: Optimize bitops with Zbb extension Xiao Wang 0 siblings, 2 replies; 6+ messages in thread From: Xiao Wang @ 2023-09-20 7:46 UTC (permalink / raw) To: paul.walmsley, palmer, aou, ardb Cc: anup, haicheng.li, ajones, linux-riscv, linux-efi, linux-kernel, Xiao Wang Bitops optimization with specialized instructions is common practice in popular ISAs, this patch set uses RISC-V Zbb extension to optimize four bitops: __ffs, __fls, ffs and fls. The first patch rearranges the content in hwcap.h cpufeature.h, it helps to avoid a cyclic header including issue for patch 2. The second patch leverages the alternative mechanism to dynamically apply this optimization. The series has following dependency: https://lore.kernel.org/linux-riscv/20230918131518.56803-8-ajones@ventanamicro.com/ Thanks, Xiao v2: - Remove the "EFI_" prefix from macro name "EFI_NO_ALTERNATIVE" to make it generic. (Ard) - patch-1 is added, it's based on "RISC-V: Enable cbo.zero in usermode". (Andrew) Xiao Wang (2): riscv: Rearrange hwcap.h and cpufeature.h riscv: Optimize bitops with Zbb extension arch/riscv/include/asm/bitops.h | 266 +++++++++++++++++++++++++- arch/riscv/include/asm/cpufeature.h | 83 ++++++++ arch/riscv/include/asm/hwcap.h | 91 --------- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 2 +- drivers/firmware/efi/libstub/Makefile | 2 +- 7 files changed, 350 insertions(+), 97 deletions(-) -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h 2023-09-20 7:46 [PATCH v2 0/2] riscv: Optimize bitops with Zbb extension Xiao Wang @ 2023-09-20 7:46 ` Xiao Wang 2023-09-20 8:29 ` Andrew Jones 2023-09-26 6:18 ` kernel test robot 2023-09-20 7:46 ` [PATCH v2 2/2] riscv: Optimize bitops with Zbb extension Xiao Wang 1 sibling, 2 replies; 6+ messages in thread From: Xiao Wang @ 2023-09-20 7:46 UTC (permalink / raw) To: paul.walmsley, palmer, aou, ardb Cc: anup, haicheng.li, ajones, linux-riscv, linux-efi, linux-kernel, Xiao Wang Now hwcap.h and cpufeature.h are mutually including each other, and most of the variable/API declarations in hwcap.h are implemented in cpufeature.c, so, it's better to move them into cpufeature.h and leave only macros for ISA extension logical IDs in hwcap.h. BTW, the riscv_isa_extension_mask macro is not used now, so this patch removes it. Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> --- arch/riscv/include/asm/cpufeature.h | 83 ++++++++++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 91 ----------------------------- arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 2 +- 5 files changed, 86 insertions(+), 93 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 13b7d35648a9..3061d33abc2f 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -7,7 +7,10 @@ #define _ASM_CPUFEATURE_H #include <linux/bitmap.h> +#include <linux/jump_label.h> #include <asm/hwcap.h> +#include <asm/alternative-macros.h> +#include <asm/errno.h> /* * These are probed via a device_initcall(), via either the SBI or directly @@ -33,4 +36,84 @@ extern struct riscv_isainfo hart_isa[NR_CPUS]; void check_unaligned_access(int cpu); void riscv_user_isa_enable(void); +unsigned long riscv_get_elf_hwcap(void); + +struct riscv_isa_ext_data { + const unsigned int id; + const char *name; + const char *property; +}; + +extern const struct riscv_isa_ext_data riscv_isa_ext[]; +extern const size_t riscv_isa_ext_count; +extern bool riscv_isa_fallback; + +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); + +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); +#define riscv_isa_extension_available(isa_bitmap, ext) \ + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) + +static __always_inline bool +riscv_has_extension_likely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_MAX, + "ext must be < RISCV_ISA_EXT_MAX"); + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + asm_volatile_goto( + ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_no); + } else { + if (!__riscv_isa_extension_available(NULL, ext)) + goto l_no; + } + + return true; +l_no: + return false; +} + +static __always_inline bool +riscv_has_extension_unlikely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_MAX, + "ext must be < RISCV_ISA_EXT_MAX"); + + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + asm_volatile_goto( + ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_yes); + } else { + if (__riscv_isa_extension_available(NULL, ext)) + goto l_yes; + } + + return false; +l_yes: + return true; +} + +static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext) +{ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext)) + return true; + + return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); +} + +static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext) +{ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext)) + return true; + + return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); +} + #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 31774bcdf1c6..141b7109c25c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,9 +8,6 @@ #ifndef _ASM_RISCV_HWCAP_H #define _ASM_RISCV_HWCAP_H -#include <asm/alternative-macros.h> -#include <asm/errno.h> -#include <linux/bits.h> #include <uapi/asm/hwcap.h> #define RISCV_ISA_EXT_a ('a' - 'a') @@ -67,92 +64,4 @@ #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA #endif -#ifndef __ASSEMBLY__ - -#include <linux/jump_label.h> -#include <asm/cpufeature.h> - -unsigned long riscv_get_elf_hwcap(void); - -struct riscv_isa_ext_data { - const unsigned int id; - const char *name; - const char *property; -}; - -extern const struct riscv_isa_ext_data riscv_isa_ext[]; -extern const size_t riscv_isa_ext_count; -extern bool riscv_isa_fallback; - -unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); - -#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) - -bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); -#define riscv_isa_extension_available(isa_bitmap, ext) \ - __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) - -static __always_inline bool -riscv_has_extension_likely(const unsigned long ext) -{ - compiletime_assert(ext < RISCV_ISA_EXT_MAX, - "ext must be < RISCV_ISA_EXT_MAX"); - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { - asm_volatile_goto( - ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) - : - : [ext] "i" (ext) - : - : l_no); - } else { - if (!__riscv_isa_extension_available(NULL, ext)) - goto l_no; - } - - return true; -l_no: - return false; -} - -static __always_inline bool -riscv_has_extension_unlikely(const unsigned long ext) -{ - compiletime_assert(ext < RISCV_ISA_EXT_MAX, - "ext must be < RISCV_ISA_EXT_MAX"); - - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { - asm_volatile_goto( - ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) - : - : [ext] "i" (ext) - : - : l_yes); - } else { - if (__riscv_isa_extension_available(NULL, ext)) - goto l_yes; - } - - return false; -l_yes: - return true; -} - -static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext) -{ - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext)) - return true; - - return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); -} - -static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext) -{ - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext)) - return true; - - return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); -} -#endif - #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index b2ba3f79cfe9..e05b5dc1f0cb 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -291,6 +291,7 @@ static inline pte_t pud_pte(pud_t pud) } #ifdef CONFIG_RISCV_ISA_SVNAPOT +#include <asm/cpufeature.h> static __always_inline bool has_svnapot(void) { diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index a727be723c56..f90d8e42f3c7 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -9,7 +9,7 @@ #include <linux/jump_label.h> #include <linux/sched/task_stack.h> #include <asm/vector.h> -#include <asm/hwcap.h> +#include <asm/cpufeature.h> #include <asm/processor.h> #include <asm/ptrace.h> #include <asm/csr.h> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index c5ee07b3df07..87aaef656257 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -15,7 +15,7 @@ #include <linux/sched.h> #include <linux/sched/task_stack.h> #include <asm/ptrace.h> -#include <asm/hwcap.h> +#include <asm/cpufeature.h> #include <asm/csr.h> #include <asm/asm.h> -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h 2023-09-20 7:46 ` [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h Xiao Wang @ 2023-09-20 8:29 ` Andrew Jones 2023-09-26 6:18 ` kernel test robot 1 sibling, 0 replies; 6+ messages in thread From: Andrew Jones @ 2023-09-20 8:29 UTC (permalink / raw) To: Xiao Wang Cc: paul.walmsley, palmer, aou, ardb, anup, haicheng.li, linux-riscv, linux-efi, linux-kernel On Wed, Sep 20, 2023 at 03:46:52PM +0800, Xiao Wang wrote: > Now hwcap.h and cpufeature.h are mutually including each other, and most of > the variable/API declarations in hwcap.h are implemented in cpufeature.c, > so, it's better to move them into cpufeature.h and leave only macros for > ISA extension logical IDs in hwcap.h. > > BTW, the riscv_isa_extension_mask macro is not used now, so this patch > removes it. > > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> Suggested-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h 2023-09-20 7:46 ` [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h Xiao Wang 2023-09-20 8:29 ` Andrew Jones @ 2023-09-26 6:18 ` kernel test robot 2023-09-26 8:39 ` Wang, Xiao W 1 sibling, 1 reply; 6+ messages in thread From: kernel test robot @ 2023-09-26 6:18 UTC (permalink / raw) To: Xiao Wang, paul.walmsley, palmer, aou, ardb Cc: oe-kbuild-all, anup, haicheng.li, ajones, linux-riscv, linux-efi, linux-kernel, Xiao Wang Hi Xiao, kernel test robot noticed the following build errors: [auto build test ERROR on linus/master] [also build test ERROR on v6.6-rc2 next-20230920] [cannot apply to efi/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Xiao-Wang/riscv-Rearrange-hwcap-h-and-cpufeature-h/20230920-154024 base: linus/master patch link: https://lore.kernel.org/r/20230920074653.2509631-2-xiao.w.wang%40intel.com patch subject: [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h config: riscv-rv32_defconfig (https://download.01.org/0day-ci/archive/20230920/202309201921.GvBmYK5q-lkp@intel.com/config) compiler: riscv32-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230920/202309201921.GvBmYK5q-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <yujie.liu@intel.com> | Closes: https://lore.kernel.org/r/202309201921.GvBmYK5q-lkp@intel.com/ All errors (new ones prefixed by >>): fs/binfmt_elf.c: In function 'create_elf_tables': >> arch/riscv/include/asm/elf.h:70:25: error: implicit declaration of function 'riscv_get_elf_hwcap'; did you mean 'riscv_fill_hwcap'? [-Werror=implicit-function-declaration] 70 | #define ELF_HWCAP riscv_get_elf_hwcap() | ^~~~~~~~~~~~~~~~~~~ fs/binfmt_elf.c:248:31: note: in definition of macro 'NEW_AUX_ENT' 248 | *elf_info++ = val; \ | ^~~ fs/binfmt_elf.c:260:31: note: in expansion of macro 'ELF_HWCAP' 260 | NEW_AUX_ENT(AT_HWCAP, ELF_HWCAP); | ^~~~~~~~~ cc1: some warnings being treated as errors -- arch/riscv/kvm/main.c: In function 'riscv_kvm_init': >> arch/riscv/kvm/main.c:73:14: error: implicit declaration of function 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] 73 | if (!riscv_isa_extension_available(NULL, h)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> arch/riscv/kvm/main.c:73:50: error: 'h' undeclared (first use in this function) 73 | if (!riscv_isa_extension_available(NULL, h)) { | ^ arch/riscv/kvm/main.c:73:50: note: each undeclared identifier is reported only once for each function it appears in cc1: some warnings being treated as errors -- arch/riscv/kvm/tlb.c: In function 'kvm_riscv_local_hfence_gvma_vmid_gpa': >> arch/riscv/kvm/tlb.c:18:25: error: implicit declaration of function 'riscv_has_extension_unlikely' [-Werror=implicit-function-declaration] 18 | #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/riscv/kvm/tlb.c:31:13: note: in expansion of macro 'has_svinval' 31 | if (has_svinval()) { | ^~~~~~~~~~~ cc1: some warnings being treated as errors -- arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_fp_reset': >> arch/riscv/kvm/vcpu_fp.c:22:13: error: implicit declaration of function 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] 22 | if (riscv_isa_extension_available(vcpu->arch.isa, f) || | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> arch/riscv/kvm/vcpu_fp.c:22:59: error: 'f' undeclared (first use in this function); did you mean 'fd'? 22 | if (riscv_isa_extension_available(vcpu->arch.isa, f) || | ^ | fd arch/riscv/kvm/vcpu_fp.c:22:59: note: each undeclared identifier is reported only once for each function it appears in >> arch/riscv/kvm/vcpu_fp.c:23:59: error: 'd' undeclared (first use in this function); did you mean 'fd'? 23 | riscv_isa_extension_available(vcpu->arch.isa, d)) | ^ | fd arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_guest_fp_save': arch/riscv/kvm/vcpu_fp.c:39:56: error: 'd' undeclared (first use in this function); did you mean 'fd'? 39 | if (riscv_isa_extension_available(isa, d)) | ^ | fd arch/riscv/kvm/vcpu_fp.c:41:61: error: 'f' undeclared (first use in this function); did you mean 'fd'? 41 | else if (riscv_isa_extension_available(isa, f)) | ^ | fd arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_guest_fp_restore': arch/riscv/kvm/vcpu_fp.c:51:56: error: 'd' undeclared (first use in this function); did you mean 'fd'? 51 | if (riscv_isa_extension_available(isa, d)) | ^ | fd arch/riscv/kvm/vcpu_fp.c:53:61: error: 'f' undeclared (first use in this function); did you mean 'fd'? 53 | else if (riscv_isa_extension_available(isa, f)) | ^ | fd arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_host_fp_save': arch/riscv/kvm/vcpu_fp.c:62:49: error: 'd' undeclared (first use in this function); did you mean 'fd'? 62 | if (riscv_isa_extension_available(NULL, d)) | ^ | fd arch/riscv/kvm/vcpu_fp.c:64:54: error: 'f' undeclared (first use in this function); did you mean 'fd'? 64 | else if (riscv_isa_extension_available(NULL, f)) | ^ | fd arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_host_fp_restore': arch/riscv/kvm/vcpu_fp.c:70:49: error: 'd' undeclared (first use in this function); did you mean 'fd'? 70 | if (riscv_isa_extension_available(NULL, d)) | ^ | fd arch/riscv/kvm/vcpu_fp.c:72:54: error: 'f' undeclared (first use in this function); did you mean 'fd'? 72 | else if (riscv_isa_extension_available(NULL, f)) | ^ | fd arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_get_reg_fp': arch/riscv/kvm/vcpu_fp.c:90:59: error: 'f' undeclared (first use in this function); did you mean 'fd'? 90 | riscv_isa_extension_available(vcpu->arch.isa, f)) { | ^ | fd arch/riscv/kvm/vcpu_fp.c:101:66: error: 'd' undeclared (first use in this function); did you mean 'fd'? 101 | riscv_isa_extension_available(vcpu->arch.isa, d)) { | ^ | fd arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_set_reg_fp': arch/riscv/kvm/vcpu_fp.c:135:59: error: 'f' undeclared (first use in this function); did you mean 'fd'? 135 | riscv_isa_extension_available(vcpu->arch.isa, f)) { | ^ | fd arch/riscv/kvm/vcpu_fp.c:146:66: error: 'd' undeclared (first use in this function); did you mean 'fd'? 146 | riscv_isa_extension_available(vcpu->arch.isa, d)) { | ^ | fd cc1: some warnings being treated as errors -- arch/riscv/kvm/vcpu_timer.c: In function 'kvm_riscv_vcpu_timer_init': >> arch/riscv/kvm/vcpu_timer.c:256:13: error: implicit declaration of function 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] 256 | if (riscv_isa_extension_available(NULL, SSTC)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> arch/riscv/kvm/vcpu_timer.c:256:49: error: 'SSTC' undeclared (first use in this function) 256 | if (riscv_isa_extension_available(NULL, SSTC)) { | ^~~~ arch/riscv/kvm/vcpu_timer.c:256:49: note: each undeclared identifier is reported only once for each function it appears in cc1: some warnings being treated as errors -- arch/riscv/kvm/vcpu_pmu.c: In function 'kvm_riscv_vcpu_pmu_init': >> arch/riscv/kvm/vcpu_pmu.c:556:14: error: implicit declaration of function 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] 556 | if (!riscv_isa_extension_available(NULL, SSCOFPMF)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> arch/riscv/kvm/vcpu_pmu.c:556:50: error: 'SSCOFPMF' undeclared (first use in this function) 556 | if (!riscv_isa_extension_available(NULL, SSCOFPMF)) | ^~~~~~~~ arch/riscv/kvm/vcpu_pmu.c:556:50: note: each undeclared identifier is reported only once for each function it appears in cc1: some warnings being treated as errors -- arch/riscv/kvm/aia.c: In function 'kvm_riscv_aia_init': >> arch/riscv/kvm/aia.c:604:14: error: implicit declaration of function 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] 604 | if (!riscv_isa_extension_available(NULL, SxAIA)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> arch/riscv/kvm/aia.c:604:50: error: 'SxAIA' undeclared (first use in this function) 604 | if (!riscv_isa_extension_available(NULL, SxAIA)) | ^~~~~ arch/riscv/kvm/aia.c:604:50: note: each undeclared identifier is reported only once for each function it appears in cc1: some warnings being treated as errors -- drivers/perf/riscv_pmu_sbi.c: In function 'pmu_sbi_setup_irqs': >> drivers/perf/riscv_pmu_sbi.c:803:13: error: implicit declaration of function 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] 803 | if (riscv_isa_extension_available(NULL, SSCOFPMF)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/perf/riscv_pmu_sbi.c:803:49: error: 'SSCOFPMF' undeclared (first use in this function) 803 | if (riscv_isa_extension_available(NULL, SSCOFPMF)) { | ^~~~~~~~ drivers/perf/riscv_pmu_sbi.c:803:49: note: each undeclared identifier is reported only once for each function it appears in cc1: some warnings being treated as errors vim +70 arch/riscv/include/asm/elf.h 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 64 2129a235c09896 Palmer Dabbelt 2017-07-10 65 /* 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 66 * Provides information on the availiable set of ISA extensions to userspace, 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 67 * via a bitmap that coorespends to each single-letter ISA extension. This is 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 68 * essentially defunct, but will remain for compatibility with userspace. 2129a235c09896 Palmer Dabbelt 2017-07-10 69 */ 50724efcb370c6 Andy Chiu 2023-06-05 @70 #define ELF_HWCAP riscv_get_elf_hwcap() 2129a235c09896 Palmer Dabbelt 2017-07-10 71 extern unsigned long elf_hwcap; 2129a235c09896 Palmer Dabbelt 2017-07-10 72 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h 2023-09-26 6:18 ` kernel test robot @ 2023-09-26 8:39 ` Wang, Xiao W 0 siblings, 0 replies; 6+ messages in thread From: Wang, Xiao W @ 2023-09-26 8:39 UTC (permalink / raw) To: Liu, Yujie, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, ardb@kernel.org Cc: oe-kbuild-all@lists.linux.dev, anup@brainfault.org, Li, Haicheng, ajones@ventanamicro.com, linux-riscv@lists.infradead.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org Hi Yujie, I would fix the riscv32 build issue in v3. I checked some *.o.cmd files from riscv64 build and see that cpufeature.h is indirectly included there, but it's not for riscv32 build. I need to change "hwcap.h" to "cpufeature.h" for all places where cpu feature detection APIs are called. Thanks for the info. BRs, Xiao > -----Original Message----- > From: Liu, Yujie <yujie.liu@intel.com> > Sent: Tuesday, September 26, 2023 2:18 PM > To: Wang, Xiao W <xiao.w.wang@intel.com>; paul.walmsley@sifive.com; > palmer@dabbelt.com; aou@eecs.berkeley.edu; ardb@kernel.org > Cc: oe-kbuild-all@lists.linux.dev; anup@brainfault.org; Li, Haicheng > <haicheng.li@intel.com>; ajones@ventanamicro.com; linux- > riscv@lists.infradead.org; linux-efi@vger.kernel.org; linux- > kernel@vger.kernel.org; Wang, Xiao W <xiao.w.wang@intel.com> > Subject: Re: [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h > > Hi Xiao, > > kernel test robot noticed the following build errors: > > [auto build test ERROR on linus/master] > [also build test ERROR on v6.6-rc2 next-20230920] > [cannot apply to efi/next] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Xiao-Wang/riscv- > Rearrange-hwcap-h-and-cpufeature-h/20230920-154024 > base: linus/master > patch link: https://lore.kernel.org/r/20230920074653.2509631-2- > xiao.w.wang%40intel.com > patch subject: [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h > config: riscv-rv32_defconfig (https://download.01.org/0day- > ci/archive/20230920/202309201921.GvBmYK5q-lkp@intel.com/config) > compiler: riscv32-linux-gcc (GCC) 13.2.0 > reproduce (this is a W=1 build): (https://download.01.org/0day- > ci/archive/20230920/202309201921.GvBmYK5q-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <yujie.liu@intel.com> > | Closes: https://lore.kernel.org/r/202309201921.GvBmYK5q- > lkp@intel.com/ > > All errors (new ones prefixed by >>): > > fs/binfmt_elf.c: In function 'create_elf_tables': > >> arch/riscv/include/asm/elf.h:70:25: error: implicit declaration of function > 'riscv_get_elf_hwcap'; did you mean 'riscv_fill_hwcap'? [-Werror=implicit- > function-declaration] > 70 | #define ELF_HWCAP riscv_get_elf_hwcap() > | ^~~~~~~~~~~~~~~~~~~ > fs/binfmt_elf.c:248:31: note: in definition of macro 'NEW_AUX_ENT' > 248 | *elf_info++ = val; \ > | ^~~ > fs/binfmt_elf.c:260:31: note: in expansion of macro 'ELF_HWCAP' > 260 | NEW_AUX_ENT(AT_HWCAP, ELF_HWCAP); > | ^~~~~~~~~ > cc1: some warnings being treated as errors > -- > arch/riscv/kvm/main.c: In function 'riscv_kvm_init': > >> arch/riscv/kvm/main.c:73:14: error: implicit declaration of function > 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] > 73 | if (!riscv_isa_extension_available(NULL, h)) { > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >> arch/riscv/kvm/main.c:73:50: error: 'h' undeclared (first use in this > function) > 73 | if (!riscv_isa_extension_available(NULL, h)) { > | ^ > arch/riscv/kvm/main.c:73:50: note: each undeclared identifier is reported > only once for each function it appears in > cc1: some warnings being treated as errors > -- > arch/riscv/kvm/tlb.c: In function 'kvm_riscv_local_hfence_gvma_vmid_gpa': > >> arch/riscv/kvm/tlb.c:18:25: error: implicit declaration of function > 'riscv_has_extension_unlikely' [-Werror=implicit-function-declaration] > 18 | #define has_svinval() > riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ > arch/riscv/kvm/tlb.c:31:13: note: in expansion of macro 'has_svinval' > 31 | if (has_svinval()) { > | ^~~~~~~~~~~ > cc1: some warnings being treated as errors > -- > arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_fp_reset': > >> arch/riscv/kvm/vcpu_fp.c:22:13: error: implicit declaration of function > 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] > 22 | if (riscv_isa_extension_available(vcpu->arch.isa, f) || > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >> arch/riscv/kvm/vcpu_fp.c:22:59: error: 'f' undeclared (first use in this > function); did you mean 'fd'? > 22 | if (riscv_isa_extension_available(vcpu->arch.isa, f) || > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c:22:59: note: each undeclared identifier is reported > only once for each function it appears in > >> arch/riscv/kvm/vcpu_fp.c:23:59: error: 'd' undeclared (first use in this > function); did you mean 'fd'? > 23 | riscv_isa_extension_available(vcpu->arch.isa, d)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_guest_fp_save': > arch/riscv/kvm/vcpu_fp.c:39:56: error: 'd' undeclared (first use in this > function); did you mean 'fd'? > 39 | if (riscv_isa_extension_available(isa, d)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c:41:61: error: 'f' undeclared (first use in this > function); did you mean 'fd'? > 41 | else if (riscv_isa_extension_available(isa, f)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_guest_fp_restore': > arch/riscv/kvm/vcpu_fp.c:51:56: error: 'd' undeclared (first use in this > function); did you mean 'fd'? > 51 | if (riscv_isa_extension_available(isa, d)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c:53:61: error: 'f' undeclared (first use in this > function); did you mean 'fd'? > 53 | else if (riscv_isa_extension_available(isa, f)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_host_fp_save': > arch/riscv/kvm/vcpu_fp.c:62:49: error: 'd' undeclared (first use in this > function); did you mean 'fd'? > 62 | if (riscv_isa_extension_available(NULL, d)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c:64:54: error: 'f' undeclared (first use in this > function); did you mean 'fd'? > 64 | else if (riscv_isa_extension_available(NULL, f)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_host_fp_restore': > arch/riscv/kvm/vcpu_fp.c:70:49: error: 'd' undeclared (first use in this > function); did you mean 'fd'? > 70 | if (riscv_isa_extension_available(NULL, d)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c:72:54: error: 'f' undeclared (first use in this > function); did you mean 'fd'? > 72 | else if (riscv_isa_extension_available(NULL, f)) > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_get_reg_fp': > arch/riscv/kvm/vcpu_fp.c:90:59: error: 'f' undeclared (first use in this > function); did you mean 'fd'? > 90 | riscv_isa_extension_available(vcpu->arch.isa, f)) { > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c:101:66: error: 'd' undeclared (first use in this > function); did you mean 'fd'? > 101 | riscv_isa_extension_available(vcpu->arch.isa, d)) { > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c: In function 'kvm_riscv_vcpu_set_reg_fp': > arch/riscv/kvm/vcpu_fp.c:135:59: error: 'f' undeclared (first use in this > function); did you mean 'fd'? > 135 | riscv_isa_extension_available(vcpu->arch.isa, f)) { > | ^ > | fd > arch/riscv/kvm/vcpu_fp.c:146:66: error: 'd' undeclared (first use in this > function); did you mean 'fd'? > 146 | riscv_isa_extension_available(vcpu->arch.isa, d)) { > | ^ > | fd > cc1: some warnings being treated as errors > -- > arch/riscv/kvm/vcpu_timer.c: In function 'kvm_riscv_vcpu_timer_init': > >> arch/riscv/kvm/vcpu_timer.c:256:13: error: implicit declaration of function > 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] > 256 | if (riscv_isa_extension_available(NULL, SSTC)) { > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >> arch/riscv/kvm/vcpu_timer.c:256:49: error: 'SSTC' undeclared (first use in > this function) > 256 | if (riscv_isa_extension_available(NULL, SSTC)) { > | ^~~~ > arch/riscv/kvm/vcpu_timer.c:256:49: note: each undeclared identifier is > reported only once for each function it appears in > cc1: some warnings being treated as errors > -- > arch/riscv/kvm/vcpu_pmu.c: In function 'kvm_riscv_vcpu_pmu_init': > >> arch/riscv/kvm/vcpu_pmu.c:556:14: error: implicit declaration of function > 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] > 556 | if (!riscv_isa_extension_available(NULL, SSCOFPMF)) > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >> arch/riscv/kvm/vcpu_pmu.c:556:50: error: 'SSCOFPMF' undeclared (first > use in this function) > 556 | if (!riscv_isa_extension_available(NULL, SSCOFPMF)) > | ^~~~~~~~ > arch/riscv/kvm/vcpu_pmu.c:556:50: note: each undeclared identifier is > reported only once for each function it appears in > cc1: some warnings being treated as errors > -- > arch/riscv/kvm/aia.c: In function 'kvm_riscv_aia_init': > >> arch/riscv/kvm/aia.c:604:14: error: implicit declaration of function > 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] > 604 | if (!riscv_isa_extension_available(NULL, SxAIA)) > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >> arch/riscv/kvm/aia.c:604:50: error: 'SxAIA' undeclared (first use in this > function) > 604 | if (!riscv_isa_extension_available(NULL, SxAIA)) > | ^~~~~ > arch/riscv/kvm/aia.c:604:50: note: each undeclared identifier is reported > only once for each function it appears in > cc1: some warnings being treated as errors > -- > drivers/perf/riscv_pmu_sbi.c: In function 'pmu_sbi_setup_irqs': > >> drivers/perf/riscv_pmu_sbi.c:803:13: error: implicit declaration of function > 'riscv_isa_extension_available' [-Werror=implicit-function-declaration] > 803 | if (riscv_isa_extension_available(NULL, SSCOFPMF)) { > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >> drivers/perf/riscv_pmu_sbi.c:803:49: error: 'SSCOFPMF' undeclared (first > use in this function) > 803 | if (riscv_isa_extension_available(NULL, SSCOFPMF)) { > | ^~~~~~~~ > drivers/perf/riscv_pmu_sbi.c:803:49: note: each undeclared identifier is > reported only once for each function it appears in > cc1: some warnings being treated as errors > > > vim +70 arch/riscv/include/asm/elf.h > > 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 64 > 2129a235c09896 Palmer Dabbelt 2017-07-10 65 /* > 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 66 * Provides information on > the availiable set of ISA extensions to userspace, > 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 67 * via a bitmap that > coorespends to each single-letter ISA extension. This is > 2350bd192fa2d9 Palmer Dabbelt 2023-02-02 68 * essentially defunct, but > will remain for compatibility with userspace. > 2129a235c09896 Palmer Dabbelt 2017-07-10 69 */ > 50724efcb370c6 Andy Chiu 2023-06-05 @70 #define ELF_HWCAP > riscv_get_elf_hwcap() > 2129a235c09896 Palmer Dabbelt 2017-07-10 71 extern unsigned long > elf_hwcap; > 2129a235c09896 Palmer Dabbelt 2017-07-10 72 > > -- > 0-DAY CI Kernel Test Service > https://github.com/intel/lkp-tests/wiki _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] riscv: Optimize bitops with Zbb extension 2023-09-20 7:46 [PATCH v2 0/2] riscv: Optimize bitops with Zbb extension Xiao Wang 2023-09-20 7:46 ` [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h Xiao Wang @ 2023-09-20 7:46 ` Xiao Wang 1 sibling, 0 replies; 6+ messages in thread From: Xiao Wang @ 2023-09-20 7:46 UTC (permalink / raw) To: paul.walmsley, palmer, aou, ardb Cc: anup, haicheng.li, ajones, linux-riscv, linux-efi, linux-kernel, Xiao Wang This patch leverages the alternative mechanism to dynamically optimize bitops (including __ffs, __fls, ffs, fls) with Zbb instructions. When Zbb ext is not supported by the runtime CPU, legacy implementation is used. If Zbb is supported, then the optimized variants will be selected via alternative patching. The legacy bitops support is taken from the generic C implementation as fallback. If the parameter is a build-time constant, we leverage compiler builtin to calculate the result directly, this approach is inspired by x86 bitops implementation. EFI stub runs before the kernel, so alternative mechanism should not be used there, this patch introduces a macro NO_ALTERNATIVE for this purpose. Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> --- arch/riscv/include/asm/bitops.h | 266 +++++++++++++++++++++++++- drivers/firmware/efi/libstub/Makefile | 2 +- 2 files changed, 264 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index 3540b690944b..c97e774cb647 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -15,13 +15,273 @@ #include <asm/barrier.h> #include <asm/bitsperlong.h> +#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) #include <asm-generic/bitops/__ffs.h> -#include <asm-generic/bitops/ffz.h> -#include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> + +#else +#include <asm/alternative-macros.h> +#include <asm/hwcap.h> + +#if (BITS_PER_LONG == 64) +#define CTZW "ctzw " +#define CLZW "clzw " +#elif (BITS_PER_LONG == 32) +#define CTZW "ctz " +#define CLZW "clz " +#else +#error "Unexpected BITS_PER_LONG" +#endif + +static __always_inline unsigned long variable__ffs(unsigned long word) +{ + int num; + + asm_volatile_goto( + ALTERNATIVE("j %l[legacy]", "nop", 0, RISCV_ISA_EXT_ZBB, 1) + : : : : legacy); + + asm volatile ( + ".option push\n" + ".option arch,+zbb\n" + "ctz %0, %1\n" + ".option pop\n" + : "=r" (word) : "r" (word) :); + + return word; + +legacy: + num = 0; +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +/** + * __ffs - find first set bit in a long word + * @word: The word to search + * + * Undefined if no set bit exists, so code should check against 0 first. + */ +#define __ffs(word) \ + (__builtin_constant_p(word) ? \ + (unsigned long)__builtin_ctzl(word) : \ + variable__ffs(word)) + +static __always_inline unsigned long variable__fls(unsigned long word) +{ + int num; + + asm_volatile_goto( + ALTERNATIVE("j %l[legacy]", "nop", 0, RISCV_ISA_EXT_ZBB, 1) + : : : : legacy); + + asm volatile ( + ".option push\n" + ".option arch,+zbb\n" + "clz %0, %1\n" + ".option pop\n" + : "=r" (word) : "r" (word) :); + + return BITS_PER_LONG - 1 - word; + +legacy: + num = BITS_PER_LONG - 1; +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; +} + +/** + * __fls - find last set bit in a long word + * @word: the word to search + * + * Undefined if no set bit exists, so code should check against 0 first. + */ +#define __fls(word) \ + (__builtin_constant_p(word) ? \ + (unsigned long)(BITS_PER_LONG - 1 - __builtin_clzl(word)) : \ + variable__fls(word)) + +static __always_inline int variable_ffs(int x) +{ + int r; + + asm_volatile_goto( + ALTERNATIVE("j %l[legacy]", "nop", 0, RISCV_ISA_EXT_ZBB, 1) + : : : : legacy); + + asm volatile ( + ".option push\n" + ".option arch,+zbb\n" + "bnez %1, 1f\n" + "li %0, 0\n" + "j 2f\n" + "1:\n" + CTZW "%0, %1\n" + "addi %0, %0, 1\n" + "2:\n" + ".option pop\n" + : "=r" (r) : "r" (x) :); + + return r; + +legacy: + r = 1; + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +/** + * ffs - find first set bit in a word + * @x: the word to search + * + * This is defined the same way as the libc and compiler builtin ffs routines. + * + * ffs(value) returns 0 if value is 0 or the position of the first set bit if + * value is nonzero. The first (least significant) bit is at position 1. + */ +#define ffs(x) (__builtin_constant_p(x) ? __builtin_ffs(x) : variable_ffs(x)) + +static __always_inline int variable_fls(unsigned int x) +{ + int r; + + asm_volatile_goto( + ALTERNATIVE("j %l[legacy]", "nop", 0, RISCV_ISA_EXT_ZBB, 1) + : : : : legacy); + + asm volatile ( + ".option push\n" + ".option arch,+zbb\n" + "bnez %1, 1f\n" + "li %0, 0\n" + "j 2f\n" + "1:\n" + CLZW "%0, %1\n" + "neg %0, %0\n" + "addi %0, %0, 32\n" + "2:\n" + ".option pop\n" + : "=r" (r) : "r" (x) :); + + return r; + +legacy: + r = 32; + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + +/** + * fls - find last set bit in a word + * @x: the word to search + * + * This is defined in a similar way as ffs, but returns the position of the most + * significant set bit. + * + * fls(value) returns 0 if value is 0 or the position of the last set bit if + * value is nonzero. The last (most significant) bit is at position 32. + */ +#define fls(x) \ + (__builtin_constant_p(x) ? \ + (int)(((x) != 0) ? \ + (sizeof(unsigned int) * 8 - __builtin_clz(x)) : 0) : \ + variable_fls(x)) + +#endif + +#include <asm-generic/bitops/ffz.h> #include <asm-generic/bitops/fls64.h> #include <asm-generic/bitops/sched.h> -#include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/hweight.h> diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile index a1157c2a7170..d68cacd4e3af 100644 --- a/drivers/firmware/efi/libstub/Makefile +++ b/drivers/firmware/efi/libstub/Makefile @@ -28,7 +28,7 @@ cflags-$(CONFIG_ARM) += -DEFI_HAVE_STRLEN -DEFI_HAVE_STRNLEN \ -DEFI_HAVE_MEMCHR -DEFI_HAVE_STRRCHR \ -DEFI_HAVE_STRCMP -fno-builtin -fpic \ $(call cc-option,-mno-single-pic-base) -cflags-$(CONFIG_RISCV) += -fpic +cflags-$(CONFIG_RISCV) += -fpic -DNO_ALTERNATIVE cflags-$(CONFIG_LOONGARCH) += -fpie cflags-$(CONFIG_EFI_PARAMS_FROM_FDT) += -I$(srctree)/scripts/dtc/libfdt -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-09-26 8:40 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-09-20 7:46 [PATCH v2 0/2] riscv: Optimize bitops with Zbb extension Xiao Wang 2023-09-20 7:46 ` [PATCH v2 1/2] riscv: Rearrange hwcap.h and cpufeature.h Xiao Wang 2023-09-20 8:29 ` Andrew Jones 2023-09-26 6:18 ` kernel test robot 2023-09-26 8:39 ` Wang, Xiao W 2023-09-20 7:46 ` [PATCH v2 2/2] riscv: Optimize bitops with Zbb extension Xiao Wang
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