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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id x13-20020aa7d38d000000b0052fe12a864esm5562105edq.57.2023.09.25.07.11.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 07:11:41 -0700 (PDT) Date: Mon, 25 Sep 2023 16:11:39 +0200 From: Andrew Jones To: Anup Patel Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry Message-ID: <20230925-e2aee59a5ea91fa14fab12ed@orel> References: <20230925133859.1735879-1-apatel@ventanamicro.com> <20230925133859.1735879-2-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230925133859.1735879-2-apatel@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230925_071146_474174_DFAD60E8 X-CRM114-Status: GOOD ( 16.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 25, 2023 at 07:08:51PM +0530, Anup Patel wrote: > Add an entry for the XVentanaCondOps extension to the > riscv,isa-extensions property. > > Signed-off-by: Anup Patel > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 36ff6749fbba..cad8ef68eca7 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -171,6 +171,13 @@ properties: > memory types as ratified in the 20191213 version of the privileged > ISA specification. > > + - const: xventanacondops > + description: | > + The Ventana specific XVentanaCondOps extension for conditional > + arithmetic and conditional-select/move operations defined by the > + Ventana custom extensions specification v1.0.1 (or higher) at > + https://github.com/ventanamicro/ventana-custom-extensions/releases. > + > - const: zba > description: | > The standard Zba bit-manipulation extension for address generation > -- > 2.34.1 > Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv